./數(shù)字電路與邏輯設(shè)計(jì)實(shí)驗(yàn)報(bào)告學(xué)院：班 級(jí)：姓 名：學(xué) 號(hào)：日期：實(shí)驗(yàn)名稱：實(shí)驗(yàn)一：QuartusII原理圖輸入法設(shè)計(jì)與實(shí)現(xiàn)實(shí)驗(yàn)二：用VHDL設(shè)計(jì)與實(shí)現(xiàn)組合邏輯電路實(shí)驗(yàn)三：用VHDL設(shè)計(jì)與實(shí)現(xiàn)時(shí)序邏輯電路實(shí)驗(yàn)四：用VHDL設(shè)計(jì)與實(shí)現(xiàn)數(shù)碼管動(dòng)態(tài)掃描控制器實(shí)驗(yàn)所用器件及儀器：1.計(jì)算機(jī)2.直流穩(wěn)壓電源3.數(shù)字系統(tǒng)與邏輯設(shè)計(jì)實(shí)驗(yàn)開(kāi)發(fā)板實(shí)驗(yàn)要求：實(shí)驗(yàn)一：用邏輯門設(shè)計(jì)實(shí)現(xiàn)一個(gè)半加器,仿真驗(yàn)證其功能,并生成新的半加器圖形模塊單元。用〔1實(shí)現(xiàn)的半加器和邏輯門設(shè)計(jì)實(shí)現(xiàn)一個(gè)全加器,仿真并驗(yàn)證其功能,并下載到實(shí)驗(yàn)板上測(cè)試。要求用撥碼開(kāi)關(guān)設(shè)定輸入信號(hào),發(fā)光二極管顯示輸出信號(hào)。用3—8線譯碼器和邏輯門設(shè)計(jì)實(shí)現(xiàn)函數(shù)F=/C/B/A+/CB/A+C/B/A+CBA,仿真驗(yàn)證其功能并下載到實(shí)驗(yàn)板測(cè)試。要求用撥碼開(kāi)關(guān)設(shè)定輸入信號(hào),發(fā)光二極管顯示輸出信號(hào)。注：實(shí)驗(yàn)時(shí)將三個(gè)元器件放在一個(gè)newblockdiagram中實(shí)現(xiàn)。實(shí)驗(yàn)二：用VHDL語(yǔ)言設(shè)計(jì)實(shí)現(xiàn)一個(gè)共陰極7段數(shù)碼譯碼器,仿真驗(yàn)證其功能,并下載到實(shí)驗(yàn)板測(cè)試。要求用撥碼開(kāi)關(guān)設(shè)定輸入信號(hào),7段數(shù)碼管顯示輸出信號(hào)。用VHDL語(yǔ)言設(shè)計(jì)實(shí)現(xiàn)一個(gè)8421碼轉(zhuǎn)余三碼的代碼器,仿真驗(yàn)證其功能,并下載到實(shí)驗(yàn)板測(cè)試。要求用撥碼開(kāi)關(guān)設(shè)定輸入信號(hào),發(fā)光二極管顯示輸出信號(hào)。用VHDL語(yǔ)言設(shè)計(jì)實(shí)現(xiàn)一個(gè)4位二進(jìn)制奇校驗(yàn)器,輸入奇數(shù)個(gè)‘1’時(shí),輸出1,否則出0；仿真驗(yàn)證其功能,并下載到實(shí)驗(yàn)板測(cè)試。要求用撥碼開(kāi)關(guān)設(shè)定輸入信號(hào),發(fā)光二極管顯示輸出信號(hào)。實(shí)驗(yàn)三：用VHDL語(yǔ)言設(shè)計(jì)實(shí)現(xiàn)一個(gè)帶異步復(fù)位的8421十進(jìn)制計(jì)數(shù)器,仿真驗(yàn)證其功能,并下載到實(shí)驗(yàn)板測(cè)試。要求用按鍵設(shè)定輸入信號(hào),發(fā)光二極管顯示輸出信號(hào)。用VHDL語(yǔ)言設(shè)計(jì)實(shí)現(xiàn)一個(gè)分頻系數(shù)為12,輸出信號(hào)占空比為50%的分頻器,仿真驗(yàn)證其功能。注：實(shí)驗(yàn)時(shí)將〔1、〔2和數(shù)碼管譯碼器3個(gè)電路進(jìn)行,并下載到實(shí)驗(yàn)板顯示計(jì)數(shù)結(jié)果。實(shí)驗(yàn)四：用VHDL語(yǔ)言設(shè)計(jì)實(shí)現(xiàn)六個(gè)數(shù)碼管串行掃描電路,要求同時(shí)顯示0,1,2,3,4,5這幾個(gè)不同的數(shù)字圖形到數(shù)碼管上,仿真驗(yàn)證其功能,并下載到實(shí)驗(yàn)板測(cè)試。用VHDL語(yǔ)言設(shè)計(jì)實(shí)現(xiàn)六個(gè)數(shù)碼管滾動(dòng)顯示電路：循環(huán)左循環(huán),左進(jìn)右出。狀態(tài)為：012345->123450->234501->345012->450123->501234->012345向左滾動(dòng),狀態(tài)為〔X表示數(shù)碼管不顯示：012345->12345X->2345XX->345XXX->45XXXX->5XXXXX->XXXXXX->XXXXX0->XXXX01->XXX012->XX0123->X01234->012345實(shí)驗(yàn)原理及設(shè)計(jì)思路：實(shí)驗(yàn)一：半加器是考慮兩位二進(jìn)制數(shù)相加,出來(lái)的結(jié)果有二者加后的一個(gè)低位數(shù),和一個(gè)這兩位數(shù)相加所得的進(jìn)位數(shù)。所以用異或門和與門即可實(shí)現(xiàn)雙輸入雙輸出的半加器。全加器可以以半加器為基礎(chǔ),在考慮兩位二進(jìn)制數(shù)相加時(shí)也考慮上地位的進(jìn)位信號(hào),輸出與半加器類似。譯碼器加邏輯門可以實(shí)現(xiàn)相應(yīng)的邏輯函數(shù),將有相應(yīng)最小項(xiàng)的輸出項(xiàng)或即可。實(shí)驗(yàn)二：共陰極7段數(shù)碼譯碼器：撥碼開(kāi)關(guān)的不同狀態(tài)對(duì)應(yīng)輸入信號(hào)的0和1,通過(guò)改變撥碼開(kāi)關(guān)的狀態(tài)改變輸入值,此時(shí)用VHDL語(yǔ)言描述每個(gè)輸入值下對(duì)應(yīng)的數(shù)在數(shù)碼管中的顯示。8421碼轉(zhuǎn)余三碼的代碼器：將8421BCD碼加上0011即為對(duì)應(yīng)的余三碼,通過(guò)通過(guò)改變撥碼開(kāi)關(guān)的狀態(tài)改變輸入的84212BCD碼,由四個(gè)LED燈的亮與滅〔亮表示該值為1,滅表示0,來(lái)表示余三碼的碼值。奇偶校驗(yàn)電路：同理用撥碼開(kāi)關(guān)設(shè)定輸入信號(hào),發(fā)光二極管顯示輸出信號(hào),輸入奇數(shù)個(gè)1時(shí),對(duì)應(yīng)的發(fā)光二極管亮,反之則為熄滅狀態(tài)。實(shí)驗(yàn)三：異步計(jì)數(shù)器：由于是異步復(fù)位,且yibuclear〔清零信號(hào)優(yōu)先級(jí)最高,當(dāng)它有效時(shí)使?fàn)顟B(tài)清零?；蛘弋?dāng)?shù)竭_(dá)第11個(gè)狀態(tài)〔1010時(shí)復(fù)位,使?fàn)顟B(tài)回歸到初始狀態(tài)〔0000。其余時(shí)刻,用cp來(lái)計(jì)數(shù),每按一次鍵cp=1,狀態(tài)加1。因此設(shè)計(jì)2個(gè)輸入端,一個(gè)輸出端數(shù)組即可。分頻器：是使cp經(jīng)過(guò)12個(gè)周期,輸出的信號(hào)正好完成一次完整的翻轉(zhuǎn),因此需要計(jì)數(shù),該計(jì)數(shù)器模值為12,每六個(gè)狀態(tài)時(shí)翻轉(zhuǎn)一次?？梢允褂梅诸l器為異步計(jì)數(shù)器提供脈沖信號(hào),異步計(jì)數(shù)器的輸出作為數(shù)碼管譯碼管的輸入,由數(shù)碼管譯碼管顯示當(dāng)前數(shù)據(jù)。實(shí)驗(yàn)四：六個(gè)數(shù)碼管串行掃描電路：由實(shí)驗(yàn)板上18號(hào)元件提供時(shí)鐘,每過(guò)一個(gè)周期,亮一個(gè)數(shù)碼管,且該數(shù)碼管序號(hào)也會(huì)改變,因此需要兩個(gè)數(shù)組來(lái)體現(xiàn)這種改變。設(shè)選擇一個(gè)管亮的數(shù)組為xuan〔5downto0,數(shù)碼管上控制輸出數(shù)字形狀的數(shù)組為guan〔6downto0,通過(guò)輸入的時(shí)鐘改變狀態(tài)〔signalstatus,由狀態(tài)定xuan,guan。由于要求"同時(shí)顯示",我們知道閃爍發(fā)光的二極管閃爍頻率較高時(shí),我們將觀察到持續(xù)點(diǎn)亮的現(xiàn)象,一個(gè)數(shù)碼管要穩(wěn)定,需要顯示頻率大于50HZ,現(xiàn)在需要6個(gè)數(shù)碼管同時(shí)顯示,因而時(shí)鐘的頻率應(yīng)該大于300HZ。六個(gè)數(shù)碼管滾動(dòng)掃描電路：大致原理同〔1,但是需要注意guan不再只有6個(gè)狀態(tài),需要用12個(gè)狀態(tài)來(lái)配合周期循環(huán)使用。需要每輪的管子狀態(tài)改變一個(gè)位移。此時(shí)可以把xuan由循環(huán)來(lái)賦值,實(shí)現(xiàn)控制不同時(shí)刻數(shù)碼管的亮與滅。實(shí)驗(yàn)?zāi)K端口及連接圖：

實(shí)驗(yàn)三〔3：分頻器的時(shí)鐘信號(hào)接外部時(shí)鐘,異步清零端接外部信號(hào),異步清零信號(hào)有效時(shí)可以實(shí)現(xiàn)分頻器部計(jì)數(shù)清零。當(dāng)外部時(shí)鐘clk=1時(shí),分頻器部計(jì)數(shù)器的狀態(tài)加1,每六個(gè)狀態(tài)clk_out實(shí)現(xiàn)一次翻轉(zhuǎn)。分頻器的輸出作為異步計(jì)數(shù)器的時(shí)鐘,異步計(jì)數(shù)器的異步復(fù)位端接外部輸入,可由實(shí)驗(yàn)板上撥碼開(kāi)關(guān)實(shí)現(xiàn)。這樣就將外部時(shí)鐘12分頻后輸入給異步計(jì)數(shù)器,異步計(jì)數(shù)器將計(jì)數(shù)輸入數(shù)碼譯碼器,實(shí)現(xiàn)控制數(shù)碼管的狀態(tài),使之顯示異步8421十進(jìn)制計(jì)數(shù)器的此刻的數(shù)。實(shí)驗(yàn)四：clk是輸入信號(hào),接外部時(shí)鐘信號(hào)〔location對(duì)應(yīng)實(shí)驗(yàn)板18,要求頻率大于300HZ,clear是異步復(fù)位信號(hào)。guan為輸出信號(hào),連接到數(shù)碼管上對(duì)應(yīng)的7條線,控制這個(gè)數(shù)碼管中每一段線的亮與滅,實(shí)現(xiàn)顯示數(shù)字。xuan是控制6個(gè)數(shù)碼管此時(shí)應(yīng)該亮哪一個(gè)。由signalstatus根據(jù)輸入信號(hào)確定此時(shí)對(duì)應(yīng)的狀態(tài)下的xuan和guan。循環(huán)左滾動(dòng)：輸入信號(hào)為clk,clear。Clear為異步復(fù)位信號(hào),Clk接外部時(shí)鐘,該時(shí)鐘共有4種頻率〔可以通過(guò)改變粉紅色按鈕上的小撥碼開(kāi)關(guān)調(diào)整,為了使實(shí)驗(yàn)現(xiàn)象符合要求,我們可以選擇最高頻率并對(duì)它進(jìn)行分頻,分出我們所需要的合適的頻率,再由分頻器輸出的信號(hào)控制狀態(tài)變化,每來(lái)一個(gè)時(shí)鐘改變一次狀態(tài),xuan和guan為輸出信號(hào),分別控制該時(shí)刻應(yīng)該亮哪個(gè)數(shù)碼管和這個(gè)數(shù)碼管上每條線的亮與滅狀態(tài)。故clk接實(shí)驗(yàn)板上18,clear可由按鍵實(shí)現(xiàn),xuan接實(shí)驗(yàn)板上cat〔0~5guan接數(shù)碼管上每條線所對(duì)應(yīng)的數(shù)字。小周期計(jì)數(shù)器控制每位數(shù)碼的顯示,大周期計(jì)數(shù)器控制數(shù)碼的移位。clk為輸入信號(hào),接外部時(shí)鐘實(shí)驗(yàn)板上18,通過(guò)循環(huán)移位及每來(lái)一個(gè)cp對(duì)xuan進(jìn)行一次賦值,選擇此時(shí)該亮的燈。通過(guò)改變輸出guan和xuan,從而得出能熄滅能亮的現(xiàn)象。guan接數(shù)碼管上的每條線所對(duì)應(yīng)位置,xuan接六個(gè)數(shù)碼管的cat端實(shí)驗(yàn)原理圖或者VHDL代碼：實(shí)驗(yàn)一〔2：其中半加器ba的原理圖如下所示：實(shí)驗(yàn)三〔3VHDL代碼如下：LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYsangeISPORT<clk:INSTD_LOGIC;clear,clearyibu:INSTD_LOGIC;b:OUTSTD_LOGIC_VECTOR<6downto0>;y2,y3,y4,y5,y6,y7:OUTSTD_LOGIC>;endsange;ARCHITECTUREaOFsangeIScomponentfenpinPORT<clk:INSTD_LOGIC;clear:INSTD_LOGIC;clk_out:OUTSTD_LOGIC>;ENDcomponent;componentyibuPORT<cp,clear:INSTD_LOGIC;q:OUTSTD_LOGIC_VECTOR<3DOWNTO0>>;ENDcomponent;componentseg7_1PORT<a:INSTD_LOGIC_VECTOR<3downto0>;b:OUTSTD_LOGIC_VECTOR<6downto0>;c,d,e,f,g,h:OUTSTD_LOGIC>;ENDcomponent;SIGNALna:STD_LOGIC;SIGNALnb:STD_LOGIC_VECTOR<3DOWNTO0>;BEGINu1:fenpinPORTMAP<clk=>clk,clear=>clear,clk_out=>na>;u2:yibuPORTMAP<cp=>na,clear=>clearyibu,q=>nb>;u3:seg7_1PORTMAP<a=>nb,b=>b,c=>y2,d=>y3,e=>y4,f=>y5,g=>y6,h=>y7>;ENDa;其中fenpin,yibu,seg7_1的VHDL代碼如下：LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYfenpinISPORT<clk:INSTD_LOGIC;clear:INSTD_LOGIC;clk_out:OUTSTD_LOGIC>;ENDfenpin;ARCHITECTUREaOFfenpinISSIGNALtmp:INTEGERRANGE0TO5;SIGNALclktmp:STD_LOGIC;BEGINPROCESS<clear,clk>BEGINIFclear='0'THENtmp<=0;ELSIF<clk'eventandclk='1'>THENIFtmp=5THENtmp<=0;clktmp<=NOTclktmp;ELSEtmp<=tmp+1;ENDIF;ENDIF;ENDPROCESS;clk_out<=clktmp;ENDa;yibu：LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYyibuISPORT<cp,clear:INSTD_LOGIC;q:OUTSTD_LOGIC_VECTOR<3DOWNTO0>>;ENDyibu;ARCHITECTUREaOFyibuISSIGNALtemp:STD_LOGIC_VECTOR<3DOWNTO0>;BEGINPROCESS<cp>BEGINIFclear='1'THENtemp<="0000";elsIFtemp="1010"THENtemp<="0000";elseIF<cp'eventandcp='1'>THENtemp<=temp+1;ENDIF;endif;ENDPROCESS;q<=temp;ENDa;LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYseg7_1ISPORT<a:INSTD_LOGIC_VECTOR<3downto0>;b:OUTSTD_LOGIC_VECTOR<6downto0>;c,d,e,f,g,h:OUTSTD_LOGIC>;數(shù)碼管譯碼器VHDL代碼：endseg7_1;ARCHITECTUREseg7_1_archOFseg7_1ISBEGINc<='0';d<='1';e<='1';f<='1';g<='1';h<='1';PROCESS<a>BEGINCASEaISWHEN"0000"=>B<="1111110";--0WHEN"0001"=>B<="0110000";--1WHEN"0010"=>B<="1101101";--2WHEN"0011"=>B<="1111001";--3WHEN"0100"=>B<="0110011";--4WHEN"0101"=>B<="1011011";--5WHEN"0110"=>B<="1011111";--6WHEN"0111"=>B<="1110000";--7WHEN"1000"=>B<="1111111";--8WHEN"1001"=>B<="1111011";--9WHENOTHERS=>B<="0000000";ENDCASE;ENDPROCESS;END;實(shí)驗(yàn)四數(shù)據(jù)管串行掃描電路：LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYchuanxingISPORT<clk,clear:INSTD_LOGIC;guan:outSTD_LOGIC_VECTOR<6downto0>;xuan:OUTSTD_LOGIC_VECTOR<5downto0>>;endchuanxing;ARCHITECTUREyuOFchuanxingISsignalstatus:integerrange0to6;BEGINprocess<clk>beginifclear='0'thenstatus<=0;elsif<clk'eventandclk='1'>thenifstatus=6thenstatus<=1;elsestatus<=status+1;endif;endif;endprocess;PROCESS<status>BEGINCASEstatusISWHEN1=>guan<="1111110";xuan<="011111";WHEN2=>guan<="0110000";xuan<="101111";WHEN3=>guan<="1101101";xuan<="110111";WHEN4=>guan<="1111001";xuan<="111011";WHEN5=>guan<="0110011";xuan<="111101";WHEN6=>guan<="1011011";xuan<="111110";WHENOTHERS=>guan<="0000000";xuan<="111111";ENDCASE;ENDPROCESS;END;循環(huán)左滾動(dòng)：LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYmoveISPORT<clk,clear:INSTD_LOGIC;guan:OUTSTD_LOGIC_VECTOR<6DOWNTO0>;xuan:OUTSTD_LOGIC_VECTOR<5DOWNTO0>>;ENDmove;ARCHITECTUREzuoOFmoveisSIGNALl:STD_LOGIC_VECTOR<6DOWNTO0>;SIGNALc:STD_LOGIC_VECTOR<5DOWNTO0>;SIGNALt,cnt1:INTEGERRANGE0TO5;SIGNALtmp:INTEGERRANGE0TO1999;signalclk1:STD_LOGIC;BEGINFenpin1:PROCESS<clk,clear>BEGINIFclear='0'THENtmp<=0;ELSIFclk'EVENTANDclk='1'THENIFtmp=1999THENtmp<=0;ELSEtmp<=tmp+1;ENDIF;ENDIF;ENDPROCESSfenpin1;fenpin2:PROCESS<tmp>BEGINIFclk'EVENTANDclk='1'THENIFtmp<1000THENclk1<='0';ELSEclk1<='1';ENDIF;ENDIF;ENDPROCESSfenpin2;change:PROCESS<clk>BEGINIF<clk'EVENTANDclk='1'>THENIF<cnt=5>THENt<=0;ELSEt<=cnt+1;ENDIF;ENDIF;ENDPROCESSchange;P0:PROCESS<clk1>BEGINIF<clk1'EVENTANDclk1='1'>THENIF<cnt1=5>THENt1<=0;ELSEt1<=cnt1+1;ENDIF;ENDIF;ENDPROCESSp0;P1:PROCESS<cnt,cnt1>BEGINIF<clear='0'>THENl<="0000000";ELSECASEt+cnt1ISWHEN0=>l<="1111110";WHEN1=>l<="0110000";WHEN2=>l<="1101101";WHEN3=>l<="1111001";WHEN4=>l<="0110011";WHEN5=>l<="1011011";WHEN6=>l<="1111110";WHEN7=>l<="0110000";WHEN8=>l<="1101101";WHEN9=>l<="1111001";WHEN10=>l<="0110011";WHEN11=>l<="1011011";WHENOTHERS=>l<="0000000";ENDCASE;ENDIF;ENDPROCESSp1;guan<=q_temp;p2:PROCESS<cnt>BEGINIF<clear='0'>THENc<="111111";ELSECASEtISWHEN0=>c<="011111";WHEN1=>c<="101111";WHEN2=>c<="110111";WHEN3=>c<="111011";WHEN4=>c<="111101";WHEN5=>c<="111110";WHENOTHERS=>c<="111111";ENDCASE;ENDIF;ENDPROCESSp2;xuan<=count;ENDzuo;亮了又熄滅：LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYbianhuaISPORT<clk,clear:INSTD_LOGIC;guan:outSTD_LOGIC_VECTOR<6downto0>;xuan:OUTSTD_LOGIC_VECTOR<5downto0>>;endbianhua;ARCHITECTUREweiOFbianhuaISsignaltmp:integerrange0to5;signalw:integerrange0to5;signals:integerrange0to10;signalk:integerrange0to1;signalo:integerrange0to6;signalp:integerrange-1to1;signalclko:std_logic_vector<0to5>;BEGINprocess<clear,clk>beginifclear='0'thentmp<=0;w<=0;s<=0;k<=0;o<=6;p<=-1;elsif<clk'eventandclk='1'>theniftmp=5thentmp<=0;w<=w+1;elsetmp<=tmp+1;endif;ifw=6thenw<=0;endif;foriin0to5loopifk=0theniftmp>=othenclko<i><='1';elsiftmp<ithenclko<i><='1';elsiftmp<i+1thenclko<i><='0';elseclko<i><='1';endif;elsifk=1thenif<5-tmp>>=othenclko<i><='1';elsiftmp<ithenclko<i><='1';elsiftmp<i+1thenclko<i><='0';elseclko<i><='1';endif;endif;endloop;iftmp=5theno<=o+p;endif;ifo=0thenk<=1;p<=1;elsifo=6thenp<=-1;k<=0;endif;foriin0to5loopxuan<i><=clko<i>;endloop;s<=tmp+w;CASEsISWHEN10=>guan<="0110011";WHEN9=>guan<="1111001";WHEN8=>guan<="1101101";WHEN7=>guan<="0110000";WHEN6=>guan<="1111110";WHEN0=>guan<="1111110";WHEN1=>guan<="0110000";WHEN2=>guan<="1101101";WHEN3=>guan<="1111001";WHEN4=>guan<="0110011";WHEN5=>guan<="1011011";ENDCASE;endif;ENDPROCESS;END;實(shí)驗(yàn)的仿真波形圖及分析：實(shí)驗(yàn)一〔2A,B為進(jìn)行加運(yùn)算的二進(jìn)制數(shù),CI為前一位數(shù)的進(jìn)位,CO是A,B相加的進(jìn)位,A,B都為1時(shí)CO=1,其余時(shí)候?yàn)榱?。S是A,B加后的最低位,A,B,CI異或而得。實(shí)驗(yàn)一〔3A,B,C為地址端,當(dāng)輸入的最小項(xiàng)在F的表達(dá)式中時(shí),F=1,其余F=0。實(shí)驗(yàn)二8421BCD碼轉(zhuǎn)為余三碼,從0000至1001,余三碼等于8421bcd碼加0011,其余情況,輸出0000；當(dāng)輸入的四位二進(jìn)制數(shù)有奇數(shù)個(gè)1時(shí)出1,其余出0；輸入0000至1001時(shí),輸出數(shù)碼管上其相應(yīng)的表現(xiàn)形式,否則數(shù)碼管沒(méi)有一根線亮?！?實(shí)驗(yàn)三外部時(shí)鐘每過(guò)6個(gè)周期,分頻器輸出翻轉(zhuǎn)一次,數(shù)碼管從顯示0開(kāi)始,直到9的對(duì)應(yīng)輸入的數(shù)據(jù)。y數(shù)組表示數(shù)碼管的選通與否,clear,yibuclear為分別為分頻器和計(jì)數(shù)器的異步復(fù)位信號(hào),當(dāng)clear=0時(shí),回到初始狀態(tài)?！卜诸l器計(jì)數(shù)從0開(kāi)始,計(jì)數(shù)器被置零。clear作用如下：<4>實(shí)