1、Resets & Interrupts Power-On Reset External Hardware Reset Crystal Monitor Computer Operating Properly Real time interruptPower On Reset Initiated by positive transition on VDD. 8192 E clock delay is built in to allow oscillator to stabilize. VDDCPU CLKDATA BUS/ADDRESS BUSIRESET8192 ECLK CyclesInter

2、nal Reset is held low by MCU For about 8192 E clocks In General: Subsystems and control bits are initialized to have least effect on system ( I.e. interrupts masked, ports read only, serial communication disabled,.) V F P P P V - VECTOR FETCHF - FREE CYCLEP - PROGRAM FETCHFFFE FFFE 1st Opcode 2nd Op

3、code 3rd Opcode 128 ECLK Cycles 64 ECLK CyclesExternal & InternalResets RESET pin asserted for 2 E clocks. RESET pin must negate before reset service can begin. No delay to stabilize oscillator. 64 ECLK CYCLES 32 ECLK CYCLESCPU CLK DATA BUS/ADDRESS BUS RESETIRESET 96 E ClocksSAMPLE PIN FFFE FFFE 1st

4、 Opcode 2nd Opcode3nd OpcodeCrystal Monitor (1 of 2)Useful for:1. Automatic Reset from a slow or stopped clock.2. Improves fault tolerance of system.Description:If the E clock drops below a frequency of 10 KHZ* and the Crystal Monitor function has been enabled, then:1. system reset is asserted on th

5、e external reset pin.2. Crystal Monitor vector is fetched. ElseEnter Self Clock Mode if Enabled* IF E CLOCK FREQUENCY 10KHz and 500KHz, THEN A CLOCK MONITOR RESET MAY OCCUR. ( NOT GUARANTEED ) Note: Crystal Monitor Time-out range 2usec - 150 usec.Crystal Monitor (2 of 2)Crystal Monitor function can

6、be enabled/ disabled at any time.PINS:1. RESET Asserted for 64 E clocks.Address Offset $0006PLLCTL - CRG PLL Control RegisterCME - Crystal Monitor Enable 1 = Monitor is enabled 0 = Monitor is disabledWhen the Crystal Monitor is enabled, a slow or stopped clocks, (including the Stop instruction) caus

7、es a crystal failure to:1. Reset the MCU (Fetch CM Vector from $FFFC-$FFFD) or2. Enter self-clock modeCrystal Loss/Stop & Reset Recovery Sequence CME = 1&SCME =0?MCU ResetsInterrupt? CME = 1&SCME =0?Stop ModeCount 8192 OSCLKSCME =1?Clock?Wait for ClockClocks ReleasedClock?MCU ResetsCount 8192 OSCLKC

8、lock?AssertSCM & SCMIFMCUEnters Self CMCount 8192 OSCLKClock?Negate SCMClocks resumeNormal OperationResumeNormal OperationClock FailedStop InstructionPower-OnYesYesNoNoYesYesYesYesYesYesNoNoNoNoNoNoNote1:Crystal Monitor Timeout Range 6 - 18.5 usNote2:Self Clock Mode Frequency Range = 2.5MHZ - 5.5MHZ

9、 Computer Operating Properly (1 of 3)Useful for:1. Insuring that the MCU does not get hung up for an extended period of time.2. Improves fault tolerance of system.Description:If the COP rate select bits are not “0” and if the watchdog timer is not reset within a specified time period:1. Then a syste

10、m reset is asserted on the external reset pin.2. COP vector is fetched ( $FFFA-$FFFB )Pins: 1. Reset - Asserted for 64E clocks. Computer Operating Properly (2 of 3)PINS1. RESET Asserted for 64 E clocksARMCOP - CRG COP Arm/Reset Timer Software writes $55 followed by $AA to ARMCOP, to reset internal C

11、OP counter.Address Offset $000EAddress Offset $0008WCOP - Window COP Mode 1 = Window COP operation (Writes to ARMCOP Register must occur in the last 25% of selected period). 0 = Normal COP operationCR2:0 - COP Watchdog Timer Rate SelectCOPCTL : Write Once in user mode, anytime in test mode. A write

12、to COPCTL will initialize COP counter .COPCTL - CRG COP Control RegisterCOP Time-out Period Select (3 OF 3)COP Rate Selection Bit DefinitionTime-Out = WindowEnd = OscClkPeriod * (OscClkDivider +3) Window-Start = OscClkPeriod * (0.75* OscClkDivider) + 9)CR2:0 = 000 - COP is OffOSCCLKCOP Divider Chain

13、Determining Reset SourceYNYSTARTCLOCKFAILSCME=1 ?ENDNASSERTRESET PINFOR 64 E-CLOCKCYCLESCLOCKMONITORSTATUS ISLATCHEDYRESET PINNEGATION,32 E-CLOCKCYCLESALLOWEDRESETPIN STILLLOW?EXTERNALLYASSERTEDRESETGO TORESETSERVICEROUTINENGO TO COPROUTINE GO TO CRYSTAL MONITORROUTINE RESETPIN STILL LOW ?CRYSTALMON

14、ITORSYSTEM RESET ?INTERRUPT EXCEPTIONSINTERRUPT STACKPRIORITIESVECTORSINTERRUPT FLOWINTERRUPT INSTRUCTIONSSTANDBY MODESInterrupt Sources From COPFromP.I.T From Crystal MonitorCOPRESETP.I.T IRQC.MRESET INTERRUPT & RESET VECTORGENERATION & PRIORITYECT IRQSSPI IRQSSCI IRQSOther IRQSResets SWI ILLOP I_V

15、ector X_VectorIPENDXPEND IRQ XIRQ RESETINTERNAL BUSEXTERNAL BUSThe MC9S12DP256can generate over 50 Interrupt requests Interrupt Stacking OrderSP before operationSP-9SP-8SP-6SP-4SP-2SPCCR D X Y PC xxNote: Stack operation is performed in 5-bus cycles even if SP is misaligned.When HCS12 acknowledges an

16、 interrupt, it stacks registers,then determines which vector to take. ( different from hc11 ).SP after operationNon-Maskable Exception Priority More than 40 interrupt sources. Separate vector for each Reset / Interrupt source. 6 Non-Maskable sources1. RESET2. Crystal Monitor*3. COP WATCHDOG*4. TRAP5

17、. XIRQ*6. SWI* Can generate external Reset * Once enabled, cannot be maskedInterrupt Vector Table (1 of 3)(64 Exception Vector Entries)Interrupt Vector Table (2 of 3)Interrupt Vector Table (3 of 3)HCS12IRQ - Masked by I-Bit in CCRXIRQ - Masked by X-Bit in CCR*IRQEN - External IRQ Enable1 = IRQ PIN i

18、s connected to interrupt logic0 = IRQ PIN is disconnected from interrupt logicIRQE - Interrupt Select Edge Sensitive1 = IRQ PIN is configured for negative edge0 = IRQ PIN is configured for level sensitiveINTCR - Interrupt Control RegisterWrite onceAddress Offset $001ENote: XIRQ and IRQ have internal

19、 pull-ups and enabled out of reset Pull-up can be turned off by clearing PUPEE in PUCR register Interrupt Request Pins Control* Once enabled, can not be maskedInterrupt & Priority ControlAn interrupt source can be elevated to highest priority( i.e. 7 ) by writing to HPRIO register ( bits 7 - 1 ). In

20、terrupt priority can only be changed when I = 1 in CCRTo promote an interrupt the user writes the least significant byte of the associated interrupt vector address to this register. If an unimplemented vector address or a non I-masked vector address (value higher than $F2) is written, then $FFF2 vec

21、tor will be the default. (highest priority interrupt).HPRIO - High Priority RegisterAddress Offset $001FInterrupt FlowHARDWAREINTERRUPTSOFTWAREINTERRUPTMASKSET?STACK MPUREGISTERCONTENTSSET I BITIN CCRLOAD INTERRUPTVECTOR INTOPROGRAM COUNTERYCONTINUE MAINPROGRAMNEXECUTE INTERRUPT SERVICE ROUTINEVECTO

22、R TABLE$FF80$FFFFInterrupt InstructionsMNEMONICOPERATIONSWIREGS MSP-9 SP1 IM PCM PCSPFFF6FFF7HLFUNCTIONSOFTWARE INTERRUPTRETURN FROM INTERRUPTRTIM REGS SP + 9 SPSPNote: RTI instruction will not unstack if another interrupt is pending.Real-Time InterruptUseful for:1. Keep track of time2. Initiate tas

23、ks on periodic bases.Description:When a time-out occurs:1. Interrupt request to CPU is generated, if enabled2. RTI vector is fetched ( $FFF0-$FFF1 )Real-Time Interrupt Flow ChartSTART ASSERTINTERRUPTENDNYNYINCREMENTINTERNALCOUNTERCOUNTIS AT ANINTERVAL ?RTIF GOES to 1RTIE=1 ?Real-Time Control/Status

24、Registers Bit 7 6 5 4 3 2 1 0Reset: 0 0 0 0 0 0 0 0RTICTL - Real-Time Clock Control RegisterAddress Offset $0007RTR6:4 - Real-Time Interrupt Prescale Rate SelectRTR3:0 - Real-Time Interrupt Modulus Counter SelectOSCCLKRTI Divider ChainNote: To initialize the internal RTI counter, write to the RTICTL

25、 register.PLL Control RegistersRTIF Real Time Interrupt FlagRTIF bit is automatically set to one at the end of every RTI period.This flag can only be cleared by writing a 1. 0 = Time-out has not yet occurred. 1 = Set when the time-out period is met.CRGFLG - CRG Flag RegisterCRGINT - CRG Interrupt Enable RegisterAddress Offset $0003Address Offset $0