1、Computer OrganizationChapter 8 Chapter 8 The center processor unitThe center processor unitChapter 8 The center processor unitChapter 8 The center processor unit8.1 The functions and functional parts of a CPU8.1 The functions and functional parts of a CPU8.2 The basic organization of the CPU8.2 The

2、basic organization of the CPU8.3 The structure of a CPU based on a accumulator8.3 The structure of a CPU based on a accumulator8.4 The structure of a CPU based on general-purpose 8.4 The structure of a CPU based on general-purpose registersregisters8.1 The functions and functional parts of a CPU8.1

3、The functions and functional parts of a CPUThe block diagram of a stored-program computerData pathControl UnitREGALUCPUmemoryI/OExternal busInternal busControl UnitData pathControl UnitControlUnit8.2 The basic organization of the CPU8.2 The basic organization of the CPUn Different instruction format

4、s require different Different instruction formats require different organizations for the CPU.organizations for the CPU.n The organization of the CPU serves as a basis for The organization of the CPU serves as a basis for classifying the computer into different classes.classifying the computer into

5、different classes.pThe 3-address and the 2-address instruction formats create The 3-address and the 2-address instruction formats create general-purpose register machines;(general-purpose register machines;(基于通用寄存器的機器基于通用寄存器的機器) )pThe one-address instruction format creates accumulator-The one-addres

6、s instruction format creates accumulator-based machines;based machines;（基于累加器的機器）（基于累加器的機器）p0-address instruction format creates stack machine.(0-address instruction format creates stack machine.(堆棧機堆棧機) )pFor the general instruction, its function of basic instruction For the general instruction, it

7、s function of basic instruction cycle is related to the structure of the CPU cycle is related to the structure of the CPU 8.2 8.2 The basic organization of the CPUThe basic organization of the CPU1 1、CPU organization based on general-purpose registersCPU organization based on general-purpose registe

8、rspA general basic instruction cycle for the A general basic instruction cycle for the register-register register-register architecture can be stated to include the following steps:architecture can be stated to include the following steps:ufetching the instructionudecoding the instructionuGenerating

9、 the effective address of the memory operand (only for load/store instructions)uFetching the source operands from registers (from memory only for a load instruction)uexecuting the operationuStoring the result into a register (into memory only for a store instruction)uIdentifying the next instruction

10、 to be fetched.8.2 8.2 The basic organization of the CPUThe basic organization of the CPU2 2、CPU organization based on an accumulatorCPU organization based on an accumulatorpIn one-address instruction format, The source address and In one-address instruction format, The source address and destinatio

11、n address are implicit, which is the accumulator.destination address are implicit, which is the accumulator.pBesides the accumulator, usually needs a small number of Besides the accumulator, usually needs a small number of other special-purpose registers, which is a source operand.other special-purp

12、ose registers, which is a source operand.pA pure accumulator-based CPU organization is simple, but it A pure accumulator-based CPU organization is simple, but it lacks generality and relies too much on memory operands.lacks generality and relies too much on memory operands.pThe performance of an acc

13、umulator-based machine can be The performance of an accumulator-based machine can be improved by adding a small set of general-purpose registers or improved by adding a small set of general-purpose registers or making use of some special-purpose registers as general-making use of some special-purpos

14、e registers as general-purpose ones in some instructions, thus reducing memory purpose ones in some instructions, thus reducing memory references.references.2 2、CPU organization based on an accumulatorCPU organization based on an accumulatorpIn an accumulator-based CPU organization, the following In

15、 an accumulator-based CPU organization, the following special-purpose registers may be useful:special-purpose registers may be useful:pStatus registerStatus registerpIntermediate registerIntermediate registerpStack-pointer registerStack-pointer registerpIndex registerIndex registerpBase registerBase

16、 register8.2 8.2 The basic organization of the CPUThe basic organization of the CPUUser-visible or instruction-accessible registerspProgram counterProgram counterpInstruction registerInstruction registerpMemory address registerMemory address registerpMemory buffer registerMemory buffer registerin CU

17、 controlling the basic instruction cycles.8.3 The structure of a CPU based on an Accumulator8.3 The structure of a CPU based on an Accumulator1 1、Design of an accumulator-based CPU built on a single Design of an accumulator-based CPU built on a single busbus單總線基于累加器的單總線基于累加器的CPUCPU框圖框圖8.3 The struct

18、ure of a CPU based on an Accumulator8.3 The structure of a CPU based on an AccumulatorDesign of an Design of an accumulator-basedaccumulator-based CPU built on a single bus CPU built on a single bus8.3 The structure of a CPU based on an Accumulator8.3 The structure of a CPU based on an Accumulator1

19、1、Design of an Design of an accumulator-basedaccumulator-based CPU built on a single bus CPU built on a single bus pTo To fetch fetch an instruction from main memory and update the an instruction from main memory and update the program counter immediately, the following three bus program counter imm

20、ediately, the following three bus transactions may be necessary:transactions may be necessary:PC-bus; bus-MAR; bus-OP1 (PC-bus; bus-MAR; bus-OP1 (為為PC+1PC+1做準備做準備) )MAR-memoryMAR-memory； memory-MBRmemory-MBR；ALU-bus-PCALU-bus-PCMBR-IRMBR-IR( If there is a dedicated path between MBR and IR, the third

21、 bus ( If there is a dedicated path between MBR and IR, the third bus cycle can be omitted. )cycle can be omitted. )lpMARlpOP1專用路徑專用路徑讀命令讀命令+1lpPCS2s1s0 = 1108.3 The structure of a CPU based on an Accumulator8.3 The structure of a CPU based on an Accumulator1 1、Design of an Design of an accumulator-

22、basedaccumulator-based CPU built on a single bus CPU built on a single bus pFor a binary operation to be executed by the ALU, For a binary operation to be executed by the ALU, a one-bus structure requires two temporary latches a one-bus structure requires two temporary latches and three bus transact

23、ions.and three bus transactions.ptwo registers that provide the source operands, OP1 and OP2, two registers that provide the source operands, OP1 and OP2, must send their data through the bus to the OP1 latch and must send their data through the bus to the OP1 latch and OP2 latch in two separate bus

24、 cycles, because in each bus OP2 latch in two separate bus cycles, because in each bus cycle, only one operand can be put on the bus.cycle, only one operand can be put on the bus.pAfter the operation, the result can be sent back to any register After the operation, the result can be sent back to any

25、 register through the bus in the third bus cycle.through the bus in the third bus cycle.8.3 The structure of a CPU based on an Accumulator8.3 The structure of a CPU based on an Accumulator2 2、Design of a 2-bus or 3-bus accumulator-based CPUDesign of a 2-bus or 3-bus accumulator-based CPUn Connecting

26、 all of the registers to a single bus makes Connecting all of the registers to a single bus makes the bus very busy and excludes any possibility of the bus very busy and excludes any possibility of parallel operations.parallel operations.n All transfer and processing operations must be done All tran

27、sfer and processing operations must be done sequentially, one at a time.sequentially, one at a time.n Performed in parallelPerformed in parallelpdedicated pathdedicated pathpparallel busesparallel buses8.3 The structure of a CPU based on an Accumulator8.3 The structure of a CPU based on an Accumulat

28、or2 2、Design of a 2-bus or 3-bus accumulator-based CPUDesign of a 2-bus or 3-bus accumulator-based CPU雙總線基于累加器的雙總線基于累加器的CPUCPU框圖框圖operation：(A) op (MBR)； (A) op (IR)； (X) op (IR)； 0 + (MBR)； 0 + (IR)； (PC) +1；(X)+1；(SP)+18.3 The structure of a CPU based on an Accumulator8.3 The structure of a CPU ba

29、sed on an Accumulator2 2、Design of a 2-bus or 3-bus accumulator-based CPUDesign of a 2-bus or 3-bus accumulator-based CPUn 1-bus-2-bus1-bus-2-bus：3 bus cycles 3 bus cycles 2 bus cycles, reduces two latches2 bus cycles, reduces two latchesn Another problem we face designing a two-bus accumulator-Anot

30、her problem we face designing a two-bus accumulator-based CPU is how to reasonably distribute the registers onto based CPU is how to reasonably distribute the registers onto the two buses.the two buses.p(A) op (MBR)(A) op (MBR)； 寄存器寄存器- -寄存器操作寄存器操作p(A) op (IR)(A) op (IR)； 寄存器寄存器- -立即數(shù)操作立即數(shù)操作p(X) op

31、(IR)(X) op (IR)；指數(shù)尋址方式中產生有效地址；指數(shù)尋址方式中產生有效地址p 0 + (MBR)0 + (MBR)； 存儲器存儲器 累加器或其他寄存器累加器或其他寄存器p0 + (IR)0 + (IR)；絕對尋址方式中送地址到；絕對尋址方式中送地址到MARMARp (PC) +1(PC) +1；(X)+1(X)+1；(SP)+1(SP)+1；更新；更新PC.X,SPPC.X,SP寄存器寄存器n 通過分析，定義總線通過分析，定義總線2 2為輔助總線，用于改進為輔助總線，用于改進ALUALU操作。操作。8.3 The structure of a CPU based on an Acc

32、umulator8.3 The structure of a CPU based on an Accumulator2 2、Design of a 2-bus or 3-bus accumulator-based CPUDesign of a 2-bus or 3-bus accumulator-based CPU三總線基于累加器的三總線基于累加器的CPUCPU框圖框圖Each execution time is a bus cycle.8.3 The structure of a CPU based on an Accumulator8.3 The structure of a CPU ba

33、sed on an Accumulator2 2、Design of a 2-bus or 3-bus accumulator-based CPUDesign of a 2-bus or 3-bus accumulator-based CPUn The four differences between the two-bus system and The four differences between the two-bus system and the three-bus system at the following:the three-bus system at the followi

34、ng:pThe additional bus, Bus3.The additional bus, Bus3.pThe removal of the result latch from the ALUThe removal of the result latch from the ALUpThe connection of the ALU output to Bus3 through the The connection of the ALU output to Bus3 through the shifter.shifter.pThe change of all registersThe ch

35、ange of all registers input connections to Bus3. input connections to Bus3.n Each operation has an execution time of 1 bus cycle.Each operation has an execution time of 1 bus cycle.8.4 The structure of a 8.4 The structure of a CPUCPU based on based on general-purposegeneral-purpose registers registe

36、rs1 1、structure of a general-purpose register setstructure of a general-purpose register setn The organization of an accumulator-based CPU can The organization of an accumulator-based CPU can be easily transformed into a CPU structure based on be easily transformed into a CPU structure based on general-purpose registers.general-purpose registers.n The registers A, Q, X, SP, are implemented as general-The register