模擬集成電路設(shè)計(jì)經(jīng)驗(yàn)總結(jié)BasicprecautionsandtipsthatanAnalogDesignershouldknow.

1.Minimumchannellengthofthetransistorshouldbefourtofivetimestheminimumfeaturesizeoftheprocess.Wedoit,tomakethelambdaofthetransistorlowi.e.therateofchangeofIdw.r.ttoVdsislow.

晶體管最小溝長(zhǎng)為工藝最小特征尺寸的4-5倍，用來(lái)減小溝長(zhǎng)調(diào)制效應(yīng)

2.Presentartofanalogdesignstillusesthetransistorinthesaturationregion.SooneshouldalwayskeepVgsoftheTransistor30%abovetheVt.

目前模擬設(shè)計(jì)仍然是使晶體管工作在飽和區(qū)，故應(yīng)使Vgs大于Vt約30%

3.Oneshouldalwayssplitthebigtransistorintosmalltransistorshavingwidthorlengthfeaturesize<or=15um.

應(yīng)把大管分成小晶體管，使其寬/長(zhǎng)特征尺寸<或=15um

4.W/LRatiooftransistorsofthemirrorcircuitshouldbelessthanorequalto5,toensurethepropermatchingofthetransistorsinthelayout.Otherwise,itresultstotheSystamaticOffsetinthecircuit.

電流鏡電路的晶體管的w/l比應(yīng)小于或等于5，以保證較好的Matching,否則會(huì)有系統(tǒng)失調(diào)5.Oneshouldmakealltherequiredpinsintheschmeticbeforegeneratingthelayoutview.Becauseit’sdiffculttoaddapininthelayoutview.AllIOpinsshouldbeametal2pinswhereasVddandGroundshouldbemetal1pins

在電路中畫(huà)出所有的管腳（pin），之后才作layout。因?yàn)樵趌ayout中增加一個(gè)pin是比較困難的。所有的IOpin應(yīng)該用metal2pin，Vdd和GND用metal1pin

6.Oneshouldfirstsimulatethecircuitwiththetypicalmodelparametersofthedevices.SinceVtofthetrasistorcanbeanythingbetweenVt(Typical)-/+20%.Sowecheckourcircuitfortheextremecasesi.e.Vt+20%,Vt-20%.AtransistorhavingVt-20%iscalledafasttransistorandtransistorhavingVt+20%iscalledslowtransistor.It’sjustawaytodifferentiatethem.Sowiththesefastandslowtransistormodelswemakefourcombinationcallednfpf,nfps,nspf,nsps,whichareknownasprocesscorners.Now,oncewearesatisfiedwiththecircuitperformancewithtypicalmodelsthanwecheckitindifferentprocesscorners,totaketheprocessvariationintoaccount.Vtisjustoneexampleoftheprocessvariationthereareothersparametertoo.

首先先用tt做電路仿真?？紤]Vt有+20%(slow)和-20%(fast),需要對(duì)工藝角考慮，F(xiàn)F，SS，F(xiàn)S，SF。除Vt，其他工藝參數(shù)也會(huì)有變化7.Itsthumbrulethatpolyresistancehasa20%processvariationwhereaswellresistancehasgot10%.ButthepolyresistancehasgotlowertemperaturecoefficentandlowerSheetResistancethanwellresistanceSowechoosetheresistancetypedependingupontherequirments.PolyCapacitancehasgotaprocessvariationof10%.多晶硅電阻大約有20%的工藝變化，而阱區(qū)電阻變化約為10%。但多晶硅電阻有較低的溫度系數(shù)和低的方塊電阻，應(yīng)根據(jù)需要來(lái)選擇電阻。多晶硅電容約有10%工藝變化8.Oneshouldalsocheckthecircuitperformancewiththetemperaturevariation.Weusulydoitfortherangeof-40Cto85C.需考慮溫度變化對(duì)電路性能的影響，通常在-40C到85C范圍

9.Oneshouldtaketheparasiticcapacitanceintoaccountwhereveroneismakinganoverlapwithmetallayersorwells有覆蓋金屬層或阱區(qū)時(shí)，須考慮寄生電容10.InLayout,alltransistorsshouldbeplacedinonedirection,toprovidethesameenvironmenttoallthetransistors.Layout中，所有晶體管統(tǒng)一擺放方向，使有相同的環(huán)境11.Oneshouldplacealltransistorinlayoutwithaduecaretothepinpositionbeforestartroutingthem.

在對(duì)晶體管布局布線之前，考慮Pin的位置

12.OneshouldalwaysusetheMetal1forhorizontalroutingandMetal2fortheverticalroutingasfaraspossible.

盡量使用metal1橫向布線，metal縱向布線

13.OneshouldneverusePOLYasroutinglayerwhentheinterconnectscarriesacurrent.Onecanhaveashortgateconnectionusingpoly.

在互連用來(lái)傳送電流時(shí)，不要用Poly來(lái)做互連。可以用poly做短的柵連接。

14.Oneshouldtrytoavoidrunningmetaloverpolygate.Asthiscausetoincreaseinparasiticcapacitance.

避免金屬在多晶硅柵上走線，會(huì)增加寄生電容

15.Currentinallthetransistorandresistorpartshouldflowinthesamedirection.

所有晶體管和電阻有相同的電流走向

16.OneshoulddothePower(Vdd&Gnd)routingintoplayermetal(metal5only).BecauseToplayermetalsareusuallythickerandwiderandsohaslowresistance.

在最上層金屬做電源（Vdd和GND）布線。因?yàn)樽钌蠈咏饘偻ǔ８瘛⒏鼘?，因而電阻較小

17.Oneshouldalwaysmergedrainandsourceoftransistor(ofsametype)connectedtogether.

merge連接的Source和Drain

18.TominimizetheprocessvariationintheResistorvalueoneshouldalwaystaketheresistor’swidththreetofourtimesofthedefaultvalue.wedoittodecreasethevalueofdifferentialofR(L)為減小工藝變化對(duì)電阻影響，應(yīng)使電阻的寬度為默認(rèn)值的3-4倍19.Oneshouldcovertheresistancewithmetallayer,toavoidthedamagedduringthewaferleveltesting.

用金屬覆蓋電阻，避免wafer級(jí)測(cè)試時(shí)的損傷

20.OneshouldalwaysmakeaCommonCentroidstructureforthematchedtransistorinthelayout.

*Eachdifferentialpairtransistorshouldbedivideintofourtransistorsandshouldbeplacedintworowscommoncentroidstructure.

*Onemayusethethelinearcommoncentroidstructureforthecurrentmirrorcircuit.

對(duì)匹配的晶體管用共中心的結(jié)構(gòu)

*差分對(duì)管，分割為4管，2*2排列，共中心

*對(duì)電流鏡，可用線形共中心

21.It’sadvisiabletoputadummylayersaroundtheresistanceandthecapacitancetoavoidtheerosionatthetimeofetching.

建議在電阻和電容周圍作dummy

22.OneshouldalwayshaveaGuardRingarroundthedifferentialpair.

在差分對(duì)周圍作保護(hù)環(huán)

23.AlwaysputaGuardRingarroundtheN-wellandP-well.

在N阱和P阱作保護(hù)環(huán)

24.Thumbruleforthemetalcurrentdensityis0.8mA/um.It’slargerforthetopmostmetallayer.

金屬電流密度0.8mA/um，最上層金屬可以更大

25.ToavoidtheLatchup,oneshouldalwaysmakethePNjunctionreversebiasedi.e.InNWELLshouldbeconnectedtopositivepowersupply(Vdd)andPWELLshouldbeconnectedtonegativepowersupply(Gnd).Designersdoittomaketheleakagecurrentsmall.

為避免Latchup，應(yīng)使PN結(jié)反偏，如N-Well應(yīng)連到正電源，P-Well應(yīng)連到負(fù)電源。這樣可減小漏電

26.It’salwaysagoodpracticetouseai