Chapter8Counters(andtheSequentialLogic)

1精選2021版課件ContentsIntroductionAnalysisoftheSequentialLogicCountersDesignofSequentialLogics2精選2021版課件8-0IntroductionThedigitalelectroniclogicisclassifiedasthecombinationallogicandthesequentiallogic.(數(shù)字電路分為：組合邏輯電路及時序邏輯電路)Thesequentiallogicincludesthecombinationallogicsectionandthememorysection.3精選2021版課件8-0IntroductionThelogicdiagramforthegeneralsequentiallogicCom-bina-tionalLogicMemoryx1xi

y1yj

q1ql

z1zk

X=(x1,x2,…,xi,)Y=(y1,y2,…,yj,)Q=(q1,q2,…,ql,)Z=(z1,z2,…,zk,)Y=F[X,Q]Z=G[X,Q]Qn+1=H[Z,Qn]OutputExp.StateExp.ExcitationExp.輸出方程驅(qū)動方程狀態(tài)方程4精選2021版課件8-0IntroductionThesequentiallogicisclassifiedastheasynchronousoneandsynchronousone(異步時序電路和同步時序電路）.Theanalysisanddesignofthesequentiallogicisdiscussedinthischapter.Andthecounteristhemostusefuldevice.5精選2021版課件8-2SynchronousCounterOperation(同步計數(shù)器）&AnalysisoftheSequentialLogic（時序電路分析）Synchronous(同步):Eventsthathaveafixedtimerelationshipwitheachother.Synchronouscounter:thecounterwhoseflip-flop(FF)areclockedatthesametimebyacommonclockpulse.6精選2021版課件8-2-1AnalysisoftheSequentialLogicWhat’sthefunctionofthefollowinglogicdiagram?Howtoanalyzethisdiagram?7精選2021版課件8-2-1AnalysisoftheSequentialLogic-ProcedureProcedure:

WritedowntheclockandexcitationexpressionsforeachFF.2.GettheirstateexpressionsbyreplacingthelogicexpressionfortheFFwithitsexcitationexpression.寫出每個觸發(fā)器的時鐘方程和驅(qū)動方程；2.將驅(qū)動方程代入觸發(fā)器的特性方程，得到狀態(tài)方程組；8精選2021版課件8-2-1AnalysisoftheSequentialLogic-Procedure3.寫出輸出方程；5.說明電路的邏輯功能。4.依次假定初態(tài),計算次態(tài),畫出狀態(tài)轉(zhuǎn)換圖(表)或時序波形圖。3.Writedowntheoutputexpression;4.Assumethepresentstate,andanalyzethenextstate,anddrawitsstatediagram(狀態(tài)轉(zhuǎn)換圖)/statesequencetable(狀態(tài)轉(zhuǎn)換表)oritstimingdiagram（時序圖）.5.Determinethelogicfunctionofthelogicdiagram.9精選2021版課件8-2-1AnalysisoftheSequentialLogic–Example1Ex.1Determinethelogicfunction.SynchronousSequentialLogicWritedowntheclockandexcitationexpressionsforeachFF.Toggleatthepositiveedge.T’FFJ=K=110精選2021版課件8-2-1AnalysisoftheSequentialLogic–Example14.Assumethepresentsate,andanalyzethenextstate,anddrawitsstatediagram/statesequencetableoritstimingdiagram.11精選2021版課件8-2-11AnalysisoftheSequentialLogic–StateSequenceTable(狀態(tài)轉(zhuǎn)換表)StateSequenceTable12精選2021版課件8-2-1AnalysisoftheSequentialLogic–StateDiagram(狀態(tài)轉(zhuǎn)換圖)00011011StateSequenceTableStateDiagramQ1Q013精選2021版課件8-2-1AnalysisoftheSequentialLogic–TimingDiagram(時序圖)TimingDiagram14精選2021版課件8-2-2A2-BitSynchronousBinaryCounter00011011A2-bitsynchronousbinarycounter(2位同步二進制/4進制加法計數(shù)器）15精選2021版課件8-2-3A3-BitSynchronousBinaryCounterEx.2Determinethelogicfunction.16精選2021版課件8-2-3A3-BitSynchronousBinaryCounter17精選2021版課件8-2-3A3-BitSynchronousBinaryCounterA3-bitsynchronousbinarycounter(3位同步二進制/8進制加法計數(shù)器）18精選2021版課件8-2-4A4-BitSynchronousDecadeCounter19精選2021版課件8-2-4A4-BitSynchronousDecadeCounter20精選2021版課件8-2-4A4-BitSynchronousDecadeCounterA1-bitsynchronousdecadecounter(同步十進制加法計數(shù)器）21精選2021版課件8-1AsynchronousCounterOperation

(異步計數(shù)器)Asynchronous:referstoeventsthatdonothaveafixedtimerelationshipwitheachotherand,generally,donotoccuratthesametime.Asynchronouscounter:counterinwhichtheFFdonotchangestatesatexactlythesametimebecausetheydonothaveacommonclockpulse.22精選2021版課件8-1-1AnalysisofAsynchronousSequentialLogicDeterminethelogicfunction.AsynchronousSequentialLogic23精選2021版課件8-1-1AnalysisofAsynchronousSequentialLogic24精選2021版課件8-1-1AnalysisofAsynchronousSequentialLogic25精選2021版課件8-1-1AnalysisofAsynchronousSequentialLogic26精選2021版課件8-1-1AnalysisofAsynchronousSequentialLogic27精選2021版課件8-1-1AnalysisofAsynchronousSequentialLogicStateSequenceTableStateDiagramAasynchronousdecadecounter(異步十進制加法計數(shù)器）28精選2021版課件8-1-2SomeUsefulConceptsValidstates(usedstates)(有效狀態(tài))statesusedbythediagraminnormaloperation.Invalidstates(unusedstates)(無效狀態(tài)）stateswhicharen’tusedbythediagraminnormaloperation.29精選2021版課件8-1-2SomeUsefulConceptsValidStatesInvalidStatesValidCycleInvalidCycle30精選2021版課件8-1-2SomeUsefulConceptsValidCycle(有效循環(huán))Cyclethatincludesthevalidstates.InvalidCycle(無效循環(huán)）Cyclethatincludestheinvalidstates.31精選2021版課件8-1-2SomeUsefulConceptsStartupautomatically(自啟動功能)Ifalogicdiagramdoesn’thaveinvalidcycle(無效循環(huán)),itcanstartupautomatically.

(電路進入無效狀態(tài)之后,在CP脈沖作用下,能自動返回有效循環(huán),稱電路能夠自啟動,否則為不能自啟動）Self-startupcheck(自啟動檢查)

Checkifalltheinvalidstatescanenterthevalidcycleautomatically.

32精選2021版課件StateDiagramStartupautomaticallySelf-startupcheck33精選2021版課件8-3Counters8-3-1CategoriesofCountersThecountercanbeclassifiedasthefollowingcategories:34精選2021版課件8-3-1CategoriesofCountersModulus-2counter(2進制）Modulus-10counter(10進制）Modulus-60counter(60進制）Modulus-Mcounter(M進制,任意進制）35精選2021版課件8-2-5SynchronousBinaryCountersQn+1=TQn+TQnC=Q0Q1Q2Q3Negativeedge-triggered36精選2021版課件8-2-5SynchronousBinaryCountersf01/2f01/4f01/8f01/16f01/16f0Thecounterisalsocalledthefrequencydivider(分頻器).C=Q0Q1Q2Q337精選2021版課件8-2-5SynchronousBinaryCounters-74161MSImodulus-16counterCounter,Divider,Modulus-16(16進制)38精選2021版課件8-2-574161MSImodulus-16counterParalleldatainputs(并行輸入端）Dataoutputs/States

ClockPulseActiveatthepositiveedgeENT,ENP:EnablePins

39精選2021版課件8-2-574161MSImodulus-16counter40精選2021版課件8-2-574161MSImodulus-16counterPresetinput(Load)(預置端）(同步預置)Active-low,synchronously

Clearinput(清零端）(異步清零)Active-low,asynchronously

41精選2021版課件8-2-574161MSImodulus-16counterAttheterminalcountof15,RCO=1.Rippleclockoutput(進位脈沖)42精選2021版課件8-2-574161MSImodulus-16counterStateDiagramTimingDiagram43精選2021版課件8-2-574161/74163MSImodulus-16counterLogicFunctionTable(功能表）for74161/7416344精選2021版課件8-2-574161/74163MSImodulus-16counterClearinput(清零端）(異步清零)Active-low,asynchronously

45精選2021版課件8-2-574161/74163MSImodulus-16counterPresetinput(Load)(預置端）(同步預置)Active-low,synchronously

46精選2021版課件8-2-574161/74163MSImodulus-16counterOnlywhenbothofEPandETareactive,isthecounterenabled(incounteroperation).Theoutputsplusoneatthepositive-edgeofCP47精選2021版課件8-2-574161/74163MSImodulus-16counterOnlywhenbothofEPandETareactive,isthecounterenabled(incounteroperation).48精選2021版課件8-2-574160MSImodulus-10counter74160synchronousBCDdecadecounter(CTRDIV10–modulus-10,10states)49精選2021版課件8-2-574160MSImodulus-10counterClearasynchronously

異步清零Theclearinputisactive-LOW.50精選2021版課件8-2-574160MSImodulus-10counterAtimingdiagramshowingthecounterbeingpresettocount7(0111).Presetsynchronously

同步預置Whenthepresetinputisnonactive,theparallelinputshavenouse.TheoutputsarepresettothecorrespondingdatainputonlyattheactiveedgeofCP.51精選2021版課件8-2-574160MSImodulus-10counterWhentheterminalcountis9(TC=9),RCO=152精選2021版課件8-2-574160MSImodulus-10counterIfanyofENPandENTisnonactive(LOW),theoutputsaredisabled,remaininpresentstates53精選2021版課件8-3Up/DownSynchronousCounters

(可逆/加減計數(shù)器)Bythecontroloftheup/downinput,thecounter,ononehand,canincreaseonebyone;ontheotherhand,canalsodecreaseonebyone.Thiskindofcounteriscalledup/down(加減)one,bidirectional

（可逆）counter,also.54精選2021版課件8-3Up/DownSynchronousCountersAbasic3-bitup/downsynchronouscounter55精選2021版課件8-3Up/DownSynchronousCountersUp/downsequencefora3-bitbinarycounterStateSequenceTablefora3-bitbinarycounter56精選2021版課件8-3Up/DownSynchronousCountersStateDiagramQ2Q1Q0000001110111010011100101UpsequenceDownsequence57精選2021版課件8-3Up/DownSynchronousCountersLogicfunctiontableforMSI74191-asynchronousmodulus-16up/downcounterPresetAsynchronously

異步預置58精選2021版課件8-3Up/DownSynchronousCountersLogicsymbolforMSI74190-asynchronousmodulus-10up/downcounter59精選2021版課件8-3Up/DownSynchronousCountersTimingExampleFora74190PresetAsynchronously

異步預置60精選2021版課件8-4DesignofSequentialLogics(時序電路設計)SequentiallogicdesignSSISequentiallogicdesign(小規(guī)模)--Designsequentiallogicusingflip-flops

用觸發(fā)器設計時序電路MSISequentiallogicdesign(中規(guī)模)--Designmodulus-McounterusingMSImodulus-Ncounter用N進制中規(guī)模集成計數(shù)器設計任意M進制計數(shù)器61精選2021版課件8-4-1SSISequentiallogicdesign-SequentialLogicsDesignusingFFProcedure:Step1:Convertthegivenproblemtoalogicproblem.Assumetheinput,outputandstatevariables.Step2:Getitsstatediagram.Step3:Getitsstatesequencetable.Step4:Accordingtothenumberofthestates,drawacorrespondingnumber-variableK-map.62精選2021版課件8-4-1SequentialLogicsDesignusingFFStep5:GetthestateexpressionsusingK-map.Step6:Choosetheneededflip-flop.

Step7:Gettheexcitationexpressionsaccordingtothestateexpressionsandlogicexpressionforthecorrespondingflip-flop.Step8:Sketchthelogicdiagram.63精選2021版課件8-4-1SequentialLogicsDesignusingFF—Example1Ex.1:Designamodulus-13counterwithcascadedoutput.Step1:Assumetheinput,outputandstatevariables.

Output:CStatevariables:S0,S1…S12Statediagram.64精選2021版課件8-4-1SequentialLogicsDesignusingFF—Example113states:4flip-fops(13<=24)Step2:Statesequencetable.65精選2021版課件8-4-1SequentialLogicsDesignusingFF—Example1Step3:next-stateK-map.Presentstate:0000Nextstate:0001Output:0Don’tcareconditions66精選2021版課件8-4-1SequentialLogicsDesignusingFF—Example1Step4:Getk-mapforeachstate.(Optional)67精選2021版課件8-4-1SequentialLogicsDesignusingFF—Example1Step5:Getthestateexpressions.68精選2021版課件8-4-1SequentialLogicsDesignusingFF—Example1Step5:Gettheoutputexpression.C=Q3?Q2Step6:Choosetheflip-flop:J-Kflip-flop.69精選2021版課件8-4-1SequentialLogicsDesignusingFF—Example1Step7:Gettheexcitationexpression.70精選2021版課件8-4-1SequentialLogicsDesignusingFF—Example1Step8:Drawthelogicdiagram.C=Q3?Q271精選2021版課件8-4-1SequentialLogicsDesignusingFF—Example1Step9:Self-startupcheck

(自啟動檢查)Itcanstartupautomatically.72精選2021版課件8-4-1SequentialLogicsDesignusingFF—Example2Ex.2:Designalogicdiagramthatcanchecktheseriesdata.WhentherearethreeormorethanthreeHIGHinputsinseries,theoutputis1;otherwise,theoutputis0.

設計一個串行數(shù)據(jù)檢測器。當連續(xù)輸入3個或3個以上1的時候，輸出為1；否則為0。

73精選2021版課件8-4-1SequentialLogicsDesignusingFF—Example2Step1:Analyzetheproblem,assumetheinput/outputvariables,andgetitsstatediagram/statesequencetable.Assume:X:theinputvariable;Y:theoutputvariable;States:S0–theinputis0; S1–thereisonlyoneHIGHinput.S2–thereistwoHIGHinputsinseries.S3–thereisthreeormorethanthreeHIGHinputsinseries.74精選2021版課件8-4-1SequentialLogicsDesignusingFF—Example2Step2:StatesequencetableEquivalentStates(等價狀態(tài))Theinput75精選2021版課件8-4-1SequentialLogicsDesignusingFF—Example2Step3:K-map0001103states:2flip-fops(3<=22)76精選2021版課件8-4-1SequentialLogicsDesignusingFF—Example277精選2021版課件8-4-1SequentialLogicsDesignusingFF—Example2Step4:StateexpressionsStep5:OutputexpressionY=X?Q178精選2021版課件8-4-1SequentialLogicsDesignusingFF—Example2Step6:Choosetheflip-flop:J-Kflip-flop.Step7:Gettheexcitationexpressions.(驅(qū)動方程)79精選2021版課件8-4-1SequentialLogicsDesignusingFF—Example2Step8:Constructthelogicdiagram.Y=X?Q180精選2021版課件8-4-1SequentialLogicsDesignusingFF—Example2Step9:Checkwhetherthediagramstartupautomatically.Itcanstartupautomatically.81精選2021版課件8-4-1SequentialLogicsDesignusingFF—Example2ImplementtheabovelogicfunctionusingDflip-flop.Y=X?Q182精選2021版課件8-4-1SequentialLogicsDesignusingFF—Example2Y=X?Q183精選2021版課件8-4-2SequentialLogicsDesignusingMSICountersAnalysisofsequentiallogicswithMSIcounters84精選2021版課件8-4-2AnalysisofSequentialLogicswithMSICounters–IUsingthepresetinputDeterminethemodulus(logicfunction)ofthegivenlogicdiagram,andthelogicfunctiontableof74160isshownasthefollowingtable.85精選2021版課件0000000100100011010001010110011110001001Modulus-7counter7進制計數(shù)器StablestateValidCycle86精選2021版課件00000001001000110110100010111100110111110100010101111001101011108-4-2AnalysisofSequentialLogicswithMSICounters–IIUsingtheclearinput87精選2021版課件0000000100100011011010001011110011011111010001010111100110101110Momentary/Astablestate瞬態(tài)/暫態(tài)Modulus-10counter10進制計數(shù)器88精選2021版課件8-4-2AnalysisofSequentialLogicswithMSICounters-IIUsingtheclearinputModulus-10counter10進制計數(shù)器Y(Q3):Cascadedoutput進位輸出端89精選2021版課件8-4-2AnalysisofSequentialLogicswithMSICounters-IIUsingtheclearinput00000001001000110110100001000101011110011010Y(Q3):Cascadedoutput90精選2021版課件8-4-2AnalysisofSequentialLogicswithMSICounters-IIUsingtheclearinputImprovedlogicdiagramusingtheclearinputCascadedoutput91精選2021版課件8-4-2AnalysisofSequentialLogicswithMSICounters–8-5(III)CascadedCountersCounterscanbeconnectedincascadetoachievehigher-modulusoperation.Cascadingmeansthatthelast-stageoutputofonecounterdrivestheinputofthenextcounter.92精選2021版課件8-5CascadedCountersThefinaloutputQ4occursonceforevery32inputclockpulses.93精選2021版課件8-5CascadedCountersTheoverallmodulusofthecascadedcountersis32,thatis,theyactasadivide-by-32counter.(整個電路為32進制計數(shù)器).Ingeneral,theoverallmodulusofcascadedcountersisequaltotheproductoftheindividualmoduli.Forinstance,theoverallmodulusofthegivencircuitis4×8=32.94精選2021版課件8-5CascadedCountersThisisasynchronouscountersinacascadedconfiguration.95精選2021版課件8-5CascadedCounters

Addition:74290MSIAsynchronousCounter96精選2021版課件97精選2021版課件8-5Addition:74290MSIAsynchronousCounter98精選2021版課件0000000100100011010001010110011110001001Q3Q2Q1Q08-5Addition:74290MSIAsynchronousCounter99精選2021版課件8-5Addition:74290MSIAsynchronousCounter100精選2021版課件8-5Addition:74290MSIAsynchronousCounter0000000100100011010010001001101010111100Q0Q3Q2Q1101精選2021版課件8-5Addition:74290MSIAsynchronousCounter102精選2021版課件Logicfunctiontablefor74290(2-5-10counter)Asynchronousclearandset-9inputs103精選2021版課件9-5CascadedCountersWhenoperationsynchronouscountersinacascadedconfiguration,itisnecessarytousethecountenableandtheterminalcountfunctionstoachievehigher-modulusoperation.Modulus-100conter104精選2021版課件8-5CascadedCounters105精選2021版課件8-4-2AnalysisofSequentialLogicswithMSICounters–IVCascadedCounterAnalysis10011010101111001101111011110000000100100011010001010110Modulus-7Modulus-6×Modulus-42(7×6)106精選2021版課件8-4-3SequentialLogicsDesignusingMSICounter

Designamodulus-McounterusingagivenMSImodulus-Ncounter.1.IfM

N,oneMSIdeviceisneeded.2.IfM>N,morethanoneMSIdeviceisneeded.107精選2021版課件8-4-3SequentialLogicsDesignusingMSICounter1.M<NSkipN-MstatesTwomethods:(1)ImplementitusingtheCLEAR(RESET)input(generallytheCLEARinputisasynchronous).(利用清零端，反饋歸零法)(2)ImplementitusingthePRESETinput.(SomeofthePRESETinputareasynchronous,andothersaresynchronous)

(利用預置端，置數(shù)法)108精選2021版課件8-4-3SequentialLogicsDesignusingMSICounterMomentary/Astablestate(瞬態(tài)),notincludedinthevalidcycle.異步清零，瞬態(tài)不包括在有效循環(huán)中Presetthestatesatanystate可在任意狀態(tài)下進行預置同步預置沒有瞬態(tài)，異頻預置有瞬態(tài)。109精選2021版課件8-4-3SequentialLogicsDesignusingMSICounterOnlywhenbothofEPandETarea