1、精品文檔加減法module addsub(input 7:0 dataa,input 7:0 datab,input add_sub,/ if this is 1, add; else subtractinput clk,output reg 8:0 result );always (posedge clk)beginif (add_sub)result = dataa + datab;/or assign cout,sum=dataa+datab;elseresult 1101，然后和8 ，亦即 1000相加就會(huì)得到5，亦即 0101 。至于溢出的最高位可以無視掉。乘法器module mul

2、t(outcome,a,b);parameter SIZE=8;inputSIZE:1 a,b;output reg2*SIZE:1 outcome;integer i;always (a or b)begin outcome=0;for(i=0,i=SIZE;i=i+1)if(bi) outcome=outcome+(a(i-1);endendmodule另一種乘法器。在初始化之際，取乘數(shù)和被乘數(shù)的正負(fù)關(guān)系，然后取被乘數(shù)和乘數(shù)的正值。輸出結(jié)果根據(jù)正負(fù)關(guān)系取得。else if( Start_Sig )case( i )0: begin精品文檔精品文檔isNeg = Multiplicand7

3、Multiplier7;Mcand = Multiplicand7 ? ( Multiplicand + 1b1 ) : Multiplicand;Mer = Multiplier7 ? ( Multiplier + 1b1 ) : Multiplier;Temp = 16d0;i = i + 1b1;end1:/ Multiplingif( Mer = 0 ) i = i + 1b1;else begin Temp = Temp + Mcand; Mer = Mer - 1b1; end2: begin isDone = 1b1; i = i + 1b1; end3: begin isDon

4、e = 1b0; i = 2d0; endendcaseassign Done_Sig = isDone;assign Product = isNeg ? ( Temp + 1b1 ) : Temp;endmodulebooth乘法器module booth_multiplier_module(input CLK,input RSTn,input Start_Sig,input 7:0A,input 7:0B,output Done_Sig,output 15:0Product,output 7:0SQ_a,output 7:0SQ_s,output 16:0SQ_p);reg 3:0i;re

5、g 7:0a;/ result of Areg 7:0s;/ reverse result of Areg 16:0p;/ p空間， 16+1位reg 3:0X;/ 指示 n 次循環(huán)reg isDone;always ( posedge CLK or negedge RSTn )if( !RSTn )begini = 4d0;a = 8d0;s = 8d0;p = 17d0;X = 4d0;精品文檔精品文檔isDone = 1b0;endelse if( Start_Sig )case( i )0:begin a = A; s = ( A + 1b1 ); p = 8d0 , B , 1b0

6、; i = i + 1b1; end1:if( X = 8 ) begin X = 4d0; i = i + 4d2; endelse if( p1:0 = 2b01 ) begin p = p16:9 + a , p8:0 ; i = i + 1b1; end else if( p1:0 = 2b10 ) begin p = p16:9 + s , p8:0 ; i = i + 1b1; endelse i = i + 1b1;/00和 11 ，無操作2:begin p = p16 , p16:1 ; X = X + 1b1; i = i - 1b1; end/ 右移，最高位補(bǔ)0 or 1.

7、3:begin isDone = 1b1; i = i + 1b1; end4:begin isDone = 1b0; i = 4d0; endendcaseassign Done_Sig = isDone;assign Product = p16:1;endmodule除法器module divider_module(input CLK,input RSTn,input Start_Sig,input 7:0Dividend,input 7:0Divisor,output Done_Sig,output 7:0Quotient,output 7:0Reminder,);reg 3:0i;re

8、g 7:0Dend;reg 7:0Dsor;reg 7:0Q;reg 7:0R;reg isNeg;reg isDone;always ( posedge CLK or negedge RSTn )if( !RSTn )begin精品文檔精品文檔i = 4d0;Dend = 8d0;Dsor = 8d0;Q = 8d0;isNeg = 1b0;isDone = 1b0;endelse if( Start_Sig )case( i )0:beginDend = Dividend7 ? Dividend + 1b1 : Dividend;Dsor = Divisor7 ? Divisor : (

9、Divisor + 1b1 );isNeg = Dividend7 Divisor7;i Dend )begin Q = isNeg ? ( Q + 1b1 ) : Q; i = i + 1b1; endelse begin Dend = Dend + Dsor; Q = Q + 1b1; end2: begin isDone = 1b1; i = i + 1b1; end3: begin isDone = 1b0; i b) begin n=a-b;m=4b0001; state=S1; endelse begin m=4b0000;n=a; state=b) begin m=m+1;n=n

10、-b;state=S1;endelse begin state=S2;endendS2: begin result=m;yu=n;state=S0;enddefule:state=S0;endcaseend精品文檔精品文檔endmodule13 、一個(gè)可預(yù)置初值的7 進(jìn)制循環(huán)計(jì)數(shù)器verilogmodule count(clk,reset,load,date,out);input load,clk,reset;input3:0 date;output reg3:0 out;parameter WIDTH=4d7;always(clk or reset)beginif(reset) out=4d

11、0;else if(load)out=date;else if(out=WIDTH-1) out=4d0;elseout=out+1;endendmoduleJohnson 計(jì)數(shù)器約翰遜 (Johnson) 計(jì)數(shù)器又稱扭環(huán)計(jì)數(shù)器,是一種用 n 位觸發(fā)器來表示 2n 個(gè)狀態(tài)的計(jì)數(shù)器。它與環(huán)形計(jì)數(shù)器不同 ,后者用 n 位觸發(fā)器僅可表示n 個(gè)狀態(tài)。 n 位二進(jìn)制計(jì)數(shù)器 (n 為觸發(fā)器的個(gè)數(shù) )有 2n個(gè)狀態(tài)。若以四位二進(jìn)制計(jì)數(shù)器為例,它可表示 16個(gè)狀態(tài)?！?000-1000-1100-1110-1111-0111-0011-0001-0000-1000 ”module Johnson(input

12、clk,input clr,output regN-1:0 q);always(posedge clk or negedge clr)if(!clr)q=N1 b0else if(!q0)q=1 b1,qN -1:1;elseq=1 b0,qN -1:1;endmodule任意分頻，占空比不為50%always(clk)beginif(count=x-1) count=0;elsecount=count+1;endassign clkout=county/y一般用 count 的最高位偶數(shù)分頻 (8 分頻，占空比 50%) （計(jì)數(shù)至 n-1 ，翻轉(zhuǎn)）module count5(reset,cl

13、k,out)input clk,reset;output out;reg1:0 count;always(clk)if(reset) begin count=0; out=0; endelse if(count=3)begin count=0;out=!out: endelse count=count+1;endmodule奇數(shù)分頻電路（占空比50% ）。module count5(reset,clk,out)input clk,reset;output out;精品文檔精品文檔reg2:0 m,n;reg count1;reg count2;always(posedge clk)begini

14、f(reset)beginm=0;count1=0;endelsebeginif(m=4) m=0; else m=m+1;/ “ 4”為分頻數(shù)NUM-1，NUM=5if(m2) count1=1; else count1=0;endendalways(negedge clk)beginif(reset)beginn=0;count2=0;endelsebeginif(n=4) n=0; else n=n+1;if(n2) count2=1; else count2=0;endendassign out=count1|count2;半整數(shù)分頻module fdiv5_5(clkin,clr,c

15、lkout)input clkin,clr; output reg clkout;reg clk1; wire clk2; integer count;xor xor1(clk2,clkin,clk1)always(posedge clkout or negedge clr)beginif(clr) begin clk1=1b0; endelse clk1=clk1;endalways(posedge clk2 or negedge clr)beginif(clr)begin count=0; clkout=1 b0; endelse if(count=5)begin count=0; clk

16、out=1b1; endelsebegin count=count+1; clkout=1b0; endendendmodule小數(shù)分頻N=M/P . N 為分配比， M 為分頻器輸入脈沖數(shù)，P 為分頻器輸出脈沖數(shù)。精品文檔精品文檔N=(8 9+9 1)/ （ 9+1 ）=8.1先做 9次 8分頻再做1次 9分頻。module fdiv8_1(clkin,rst,clkout)input clkin,rst; output reg clkout;reg3:0 cnt1,cnt2;always(posedge clkin or posedge rst)begin if(rst) begin cn

17、t1=0;cnt2=0;clkout=0; endelse if(cnt19)/cnt1,08beginif(cnt27) begin cnt2=cnt2+1;clkout=0; endelse begin cnt2=0;cnt1=cnt1+1;clkout=1; endendelse begin/cnt1,9if(cnt28) begin cnt2=cnt2+1;clkout=0; endelsebegin cnt2=0;cnt1=0;clkout=1;endendendendmodule串并轉(zhuǎn)換module p2s(clk,clr,load,pi,so)input clk,clr,load

18、;input 3:0 pi;output so;reg3:0 r;always(posedge clk or negedge clr)if(clr)r=4h0;else if(load)r=pi;else r=r,1b0; / or r1;assign so=r3;endmodulemodule s2p(clk,clr,en,si,po)input clk,clr,en,si;output3:0 po;always(posedge clk or negedge clr)if(clr)r= 8 ho;elser=r,si;assign po=(en) ? r : 4 h0;endmoduleb)

19、試用 VHDL或 VERILOG 、ABLE 描述 8 位 D 觸發(fā)器邏輯。module dff(q,qn,d,clk,set,reset)input7:0 d,set;input clk,reset;output reg7:0 q,qn;always (posedge clk)精品文檔精品文檔beginif(reset) begin q=8 h00; qn=8 hFF;endelse if(set) beginq=8 hFF; qn=8 h00;endelse begin q=d; qn=d; endendendmodule序列檢測(cè)“ 101 ”module xulie101(clk,clr

20、,x,z);input clk,clr,x;output reg z;reg1:0 state,next_state;parameter s0=2b00,s1=2b01,s2=2b11,s3=2b10;always (posedge clk or posedge clr)begin if(clr) state=s0;else state=next_state;endalways (state or x)begincase(state)s0:begin if(x)next_state=s1;elsenext_state=s0;ends1:begin if(x)next_state=s1;else

21、next_state=s2;ends2:begin if(x)next_state=s3;elsenext_state=s0;ends3:begin if(x)next_state=s1;elsenext_state=s2;enddefault: next_state=s0;endcaseendalways (state)begincase(state)s3:z=1;default:z=0;endcaseendendmodule按鍵消抖1. 采用一個(gè)頻率較低的時(shí)鐘，對(duì)輸入進(jìn)行采樣，消除抖動(dòng)。精品文檔精品文檔module switch(clk,keyin,keyout)parameter COU

22、NTWIDTH=8;input clk,keyin;output reg keyout;regCOUNTWIDTH-1:0 counter;wire clk_use;/頻率較低的時(shí)鐘assignclk_use=counterCOUNTWIDTH-1;always(posegde clk)counter=counter+1 b1;always(posedge clk_use)keyout=keyin;endmodule2. module switch(clk,keyin,keyout) parameter COUNTWIDTH=8;input clk,keyin;output reg keyou

23、t;regCOUNTWIDTH-1:0 counter;initialcounter=0,keyout=0,keyin=0;always(posegde clk)if(keyin=1) begin key_m=keyin, counter=counter+1;endelse counter=0;if(keyin&counterm) keyout=1;/m 定義時(shí)延endmodule數(shù)碼管顯示module number_mod_module/ 分別取得數(shù)字的十位和個(gè)位(CLK, RSTn, Number_Data, Ten_Data, One_Data);input CLK;input RSTn

24、;input 7:0Number_Data;output 3:0Ten_Data;output 3:0One_Data;reg 31:0rTen;reg 31:0rOne;always ( posedge CLK or negedge RSTn )if( !RSTn )beginrTen = 32d0;rOne = 32d0;endelsebeginrTen = Number_Data / 10;rOne = Number_Data % 10;endassign Ten_Data = rTen3:0;assign One_Data = rOne3:0;endmodule精品文檔精品文檔modu

25、le led(CLK, Ten_Data, One_Data,led0, led1);/ 數(shù)碼管顯示input 3:0 Ten_Data, One_Data;input CLK;output 7:0 led0, led1;reg7:0 led0, led1;always( posedge cp_50)begincasez (One_Data)4d0 : led0 = 8b1100_0000;4d1 : led0 = 8b1111_1001;4d2 : led0 = 8b1010_0100;4d3 : led0 = 8b1011_0000;4d4 : led0 = 8b1001_1001;4d5

26、 : led0 = 8b1001_0010;4d6 : led0 = 8b1000_0010;4d7 : led0 = 8b1111_1000;4d8 : led0 = 8b1000_0000;4d9 : led0 = 8b1001_0000;default:led0 = 8b1111_1111;endcasecasez (Ten_Data)4d0 : led1 = 8b1100_0000;4d1 : led1 = 8b1111_1001;4d2 : led1 = 8b1010_0100;4d3 : led1 = 8b1011_0000;4d4 : led1 = 8b1001_1001;4d5

27、 : led1 = 8b1001_0010;4d6 : led1 = 8b1000_0010;4d7 : led1 = 8b1111_1000;4d8 : led1 = 8b1000_0000;4d9 : led1 = 8b1001_0000;default:led0 = 8b1111_1111;endcaseendendmodule5. fifo控制器 .FIFO 存儲(chǔ)器FIFO 是英文 First In FirstOut的縮寫，是一種先進(jìn)先出的數(shù)據(jù)緩存器，他與普通存儲(chǔ)器的區(qū)別是沒有外部讀寫地址線，這樣使用起來非常簡單，但缺點(diǎn)就是只能順序?qū)懭霐?shù)據(jù)，順序的讀出數(shù)據(jù)，其數(shù)據(jù)地址由內(nèi)部讀寫指針自動(dòng)

28、加1 完成，不能像普通存儲(chǔ)器那樣可以由地址線決定讀取或?qū)懭肽硞€(gè)指定的地址。 在系統(tǒng)設(shè)計(jì)中，以增加數(shù)據(jù)傳輸率、處理大量數(shù)據(jù)流、匹配具有不同傳輸率的系統(tǒng)為目的而廣泛使用 FIFO 存儲(chǔ)器，從而提高了系統(tǒng)性能 .FIFO 參數(shù)：FIFO 的寬度， the width，指 FIFO 一次讀寫操作的數(shù)據(jù)位；FIFO 深度， THE DEEPTH ，指 FIFO 可以存儲(chǔ)多少個(gè)N 位的數(shù)據(jù)；精品文檔精品文檔滿標(biāo)志， FIFO 已滿或?qū)⒁獫M時(shí)送出的一個(gè)信號(hào)，以阻止FIFO 的血操作繼續(xù)向FIFO 中寫數(shù)據(jù)而造成溢出（ overflow ）；空標(biāo)志，阻止FIFIO 的讀操作；module fifo_modul

29、e(input CLK,input RSTn,input Write_Req,input 7:0FIFO_Write_Data,input Read_Req,output 7:0FIFO_Read_Data,output Full_Sig,output Empty_Sig,/*/output 7:0SQ_rS1,output 7:0SQ_rS2,output 7:0SQ_rS3,output 7:0SQ_rS4,output 2:0SQ_Count/*/);/*/parameter DEEP = 3d4;/*/reg 7:0rShift DEEP:0;reg 2:0Count;reg 7:0D

30、ata;always ( posedge CLK or negedge RSTn )if( !RSTn )beginrShift0 = 8d0; rShift1 = 8d0; rShift2 = 8d0;rShift3 = 8d0; rShift4 = 8d0;Count = 3d0;Data = 8d0;endelse if( Read_Req & Write_Req & Count 0 )beginrShift1 = FIFO_Write_Data;rShift2 = rShift1;rShift3 = rShift2;rShift4 = rShift3;Data = rShift Cou

31、nt ;end精品文檔精品文檔else if( Write_Req & Count DEEP )beginrShift1 = FIFO_Write_Data;rShift2 = rShift1;rShift3 = rShift2;rShift4 = rShift3;Count 0 )beginData = rShiftCount;Count = Count - 1b1;end/*/assign FIFO_Read_Data = Data;assign Full_Sig = ( Count = DEEP ) ? 1b1 : 1b0;assign Empty_Sig = ( Count = 0 )

32、 ? 1b1 : 1b0;/*/assign SQ_rS1 = rShift1;assign SQ_rS2 = rShift2;assign SQ_rS3 = rShift3;assign SQ_rS4 = rShift4;assign SQ_Count = Count;/*/Endmodulefifi 2(指針控制 )module FIFO(date,q,clr,clk,we,re,ff,ef);parameter WIDTH=8,DEEPTH=8,ADDR=3;input clk,clr;input we,re;inputWIDTH-1:0 date;output ff,ef;output

33、 regWIDTH-1:0 q;regWIDTH-1:0 mem_dateDEEPTH-1:0;regADDR-1:0 waddr,raddr;reg ff,ef;always(posedge clk or negedge clr)/ 寫地址begin if(!clr) waddr=0;else if(we=1&ff=0) waddr=waddr+1;else if(we=1&ff=0&waddr=7) waddr=0;endalways(posedge clk)begin if(we&!ff) mem_datewaddr=date;end精品文檔精品文檔always(posedge clk

34、or negedge clr)/ 讀地址begin if(!clr) raddr=0;else if(re=1&ef=0) raddr=waddr+1;else if(re=1&ef=0&raddr=7) raddr=0;endalways(posedge clk)begin if(re&!ef) q=mem_dateraddr; endalways(posedge clk or negedge clr)begin if(!clr) ff=1b0;else if(we & !re) & (waddr=raddr-1) | (waddr=DEEPTH-1) & (raddr=1b0)ff=1b1;elseff=1b0;endalways(posedge clk or negedge clr)begin if(!clr) ef=1b0;