王金明：《VerilogHDL程序設(shè)計(jì)教程》-1-【例3.1】4位全加器moduleadder4(cout,sum,ina,inb,cin);output[3:0]sum;outputcout;input[3:0]ina,inb;inputcin;assign{cout,sum}=ina+inb+cin;endmodule【例3.2】4位計(jì)數(shù)器modulecount4(out,reset,clk);output[3:0]out;inputreset,clk;reg[3:0]out;always@(posedgeclk)beginif(reset)out<=0;//同步復(fù)位elseout<=out+1;//計(jì)數(shù)endendmodule【例3.3】4位全加器的仿真程序`timescale1ns/1ns`include"adder4.v"moduleadder_tp;//測試模塊的名字reg[3:0]a,b;//測試輸入信號定義為reg型regcin;wire[3:0]sum;//測試輸出信號定義為wire型wirecout;integeri,j;adder4adder(sum,cout,a,b,cin);//調(diào)用測試對象always#5cin=~cin;//設(shè)定cin的取值initialbegina=0;b=0;cin=0;for(i=1;i<16;i=i+1)#10a=i;//設(shè)定a的取值Endinitialbeginfor(j=1;j<16;j=j+1)#10b=j;//設(shè)定b的取值Endinitial//定義結(jié)果顯示格式begin$monitor($time,,,"%d+%d+%b={%b,%d}",a,b,cin,cout,sum);#160$finish;endendmodule【例3.4】4位計(jì)數(shù)器的仿真程序`timescale1ns/1ns`include"count4.v"modulecoun4_tp;regclk,reset;//測試輸入信號定義為reg型wire[3:0]out;//測試輸出信號定義為wire型parameterDELY=100;count4mycount(out,reset,clk);//調(diào)用測試對象always#(DELY/2)clk=~clk;//產(chǎn)生時鐘波形initialbegin//激勵信號定義clk=0;reset=0;#DELYreset=1;#DELYreset=0;#(DELY*20)$finish;end//定義結(jié)果顯示格式initial$monitor($time,,,"clk=%dreset=%dout=%d",clk,reset,out);endmodule【例3.5】“與-或-非”門電路moduleAOI(A,B,C,D,F);//模塊名為AOI(端口列表A，B，C，D，F(xiàn))inputA,B,C,D;//模塊的輸入端口為A，B，C，DoutputF;//模塊的輸出端口為FwireA,B,C,D,F;//定義信號的數(shù)據(jù)類型assignF=~((A&B)|(C&D));//邏輯功能描述endmodule【例5.1】用case語句描述的4選1數(shù)據(jù)選擇器modulemux4_1(out,in0,in1,in2,in3,sel);outputout;inputin0,in1,in2,in3;input[1:0]sel;regout;always@(in0orin1orin2orin3orsel)//敏感信號列表case(sel)2'b00:out=in0;2'b01:out=in1;2'b10:out=in2;2'b11:out=in3;default:out=2'bx;endcaseendmodule【例5.2】同步置數(shù)、同步清零的計(jì)數(shù)器modulecount(out,data,load,reset,clk);output[7:0]out;input[7:0]data;inputload,clk,reset;reg[7:0]out;always@(posedgeclk)//clk上升沿觸發(fā)beginif(!reset)out=8'h00;//同步清0，低電平有效elseif(load)out=data;//同步預(yù)置elseout=out+1;//計(jì)數(shù)endendmodule【例5.4】用initial過程語句對測試變量A、B、C賦值`timescale1ns/1nsmoduletest;regA,B,C;initialbeginA=0;B=1;C=0;#50A=1;B=0;#50A=0;C=1;#50B=1;#50B=0;C=0;#50$finish;endendmodule【例5.5】用begin-end串行塊產(chǎn)生信號波形`timescale10ns/1nsmodulewave1;regwave;parametercycle=10;initialbeginwave=0;#(cycle/2)wave=1;#(cycle/2)wave=0;#(cycle/2)wave=1;#(cycle/2)wave=0;#(cycle/2)wave=1;#(cycle/2)$finish;endinitial$monitor($time,,,"wave=%b",wave);endmodule【例5.6】用fork-join并行塊產(chǎn)生信號波形`timescale10ns/1nsmodulewave2;regwave;parametercycle=5;initialforkwave=0;#(cycle)wave=1;#(2*cycle)wave=0;#(3*cycle)wave=1;#(4*cycle)wave=0;#(5*cycle)wave=1;#(6*cycle)$finish;joininitial$monitor($time,,,"wave=%b",wave);endmodule【例5.7】持續(xù)賦值方式定義的2選1多路選擇器moduleMUX21_1(out,a,b,sel);inputa,b,sel;outputout;assignout=(sel==0)?a:b;//持續(xù)賦值，如果sel為0，則out=a；否則out=bEndmodule【例5.8】阻塞賦值方式定義的2選1多路選擇器moduleMUX21_2(out,a,b,sel);inputa,b,sel;outputout;regout;always@(aorborsel)beginif(sel==0)out=a;//阻塞賦值elseout=b;endendmodule【例5.9】非阻塞賦值modulenon_block(c,b,a,clk);outputc,b;inputclk,a;regc,b;always@(posedgeclk)beginb<=a;c<=b;endendmodule【例5.10】阻塞賦值moduleblock(c,b,a,clk);outputc,b;inputclk,a;regc,b;always@(posedgeclk)beginb=a;c=b;endendmodule`timescale1ns/1ns`include"block.v"moduleblock_tb; wirec,b; regclk,a; initial begin clk=0;a=0; #30a=1; #30a=0; #30a=1; #30$stop; end always#10clk=~clk; blockblock(.c(c),.b(b),.clk(clk),.a(a)); endmodule【例5.13】用casez描述的數(shù)據(jù)選擇器modulemux_casez(out,a,b,c,d,select);outputout;inputa,b,c,d;input[3:0]select;regout;always@(selectoraorborcord)begincasez(select)4'b???1:out=a;4'b??1?:out=b;4'b?1??:out=c;4'b1???:out=d;endcaseendendmodule【例5.15】用for語句描述的七人投票表決器modulevoter7(pass,vote);outputpass;input[6:0]vote;reg[2:0]sum;integeri;regpass;always@(vote)beginsum=0;-9-for(i=0;i<=6;i=i+1)//for語句if(vote[i])sum=sum+1;if(sum[2])pass=1;//若超過4人贊成，則pass=1elsepass=0;endendmodule【例5.16】用for語句實(shí)現(xiàn)2個8位數(shù)相乘modulemult_for(outcome,a,b);parametersize=8;input[size:1]a,b;//兩個操作數(shù)output[2*size:1]outcome;//結(jié)果reg[2*size:1]outcome;integeri;always@(aorb)beginoutcome=0;for(i=1;i<=size;i=i+1)//for語句if(b[i])outcome=outcome+(a<<(i-1));endendmodule【例5.17】用repeat實(shí)現(xiàn)8位二進(jìn)制數(shù)的乘法modulemult_repeat(outcome,a,b);parametersize=8;input[size:1]a,b;output[2*size:1]outcome;reg[2*size:1]temp_a,outcome;reg[size:1]temp_b;always@(aorb)beginoutcome=0;temp_a=a;temp_b=b;repeat(size)//repeat語句，size為循環(huán)次數(shù)beginif(temp_b[1])//如果temp_b的最低位為1，就執(zhí)行下面的加法outcome=outcome+temp_a;temp_a=temp_a<<1;//操作數(shù)a左移一位程序文本-10-temp_b=temp_b>>1;//操作數(shù)b右移一位endendendmodule`include"mult_repeat.v"modulemult_repeat_tb; parametersize=8; reg[size:1]a,b; wire[2*size:1]outcome; initial begin a=8'h25;b=8'h16; #10a=8'ha4;b=8'h20; end mult_repeatmult(.a(a),.b(b),.outcome(outcome)); endmodule【例5.19】使用了`include語句的16位加法器-11-`include"adder.v"moduleadder16(cout,sum,a,b,cin);outputcout;parametermy_size=16;output[my_size-1:0]sum;input[my_size-1:0]a,b;inputcin;addermy_adder(cout,sum,a,b,cin);//調(diào)用adder模塊endmodule//下面是adder模塊代碼moduleadder(cout,sum,a,b,cin);parametersize=16;outputcout;output[size-1:0]sum;inputcin;input[size-1:0]a,b;assign{cout,sum}=a+b+cin;endmodule【例5.20】條件編譯舉例modulecompile(out,A,B);outputout;inputA,B;`ifdefadd//宏名為addassignout=A+B;`elseassignout=A-B;`endifEndmodule【例6.2】任務(wù)舉例modulealutask(code,a,b,c);input[1:0]code;input[3:0]a,b;output[4:0]c;reg[4:0]c;taskmy_and;//任務(wù)定義，注意無端口列表input[3:0]a,b;//a,b,out名稱的作用域范圍為task任務(wù)內(nèi)部output[4:0]out;integeri;beginfor(i=3;i>=0;i=i-1)out[i]=a[i]&b[i];//按位與endendtaskalways@(codeoraorb)begincase(code)2'b00:my_and(a,b,c);/*調(diào)用任務(wù)my_and，需注意端口列表的順序應(yīng)與任務(wù)定義中的一致，這里的a,b,c分別對應(yīng)任務(wù)定義中的a,b,out*/2'b01:c=a|b;//或2'b10:c=a-b;//相減2'b11:c=a+b;//相加endcaseendendmodule-13-【例6.3】測試程序`include"alutask.v"modulealu_tp;reg[3:0]a,b;reg[1:0]code;wire[4:0]c;parameterDELY=100;alutaskADD(code,a,b,c);//調(diào)用被測試模塊initialbegincode=4'd0;a=4'b0000;b=4'b1111;#DELYcode=4'd0;a=4'b0111;b=4'b1101;#DELYcode=4'd1;a=4'b0001;b=4'b0011;#DELYcode=4'd2;a=4'b1001;b=4'b0011;#DELYcode=4'd3;a=4'b0011;b=4'b0001;#DELYcode=4'd3;a=4'b0111;b=4'b1001;#DELY$finish;endinitial$monitor($time,,,"code=%ba=%bb=%bc=%b",code,a,b,c);endmodule【例6.4】函數(shù)function[7:0]get0;input[7:0]x;reg[7:0]count;integeri;begincount=0;for(i=0;i<=7;i=i+1)if(x[i]=1'b0)count=count+1;get0=count;endendfunction【例6.5】用函數(shù)和case語句描述的編碼器（不含優(yōu)先順序）modulecode_83(din,dout);input[7:0]din;output[2:0]dout;程序文本-14-function[2:0]code;//函數(shù)定義input[7:0]din;//函數(shù)只有輸入，輸出為函數(shù)名本身casex(din)8'b1xxx_xxxx:code=3'h7;8'b01xx_xxxx:code=3'h6;8'b001x_xxxx:code=3'h5;8'b0001_xxxx:code=3'h4;8'b0000_1xxx:code=3'h3;8'b0000_01xx:code=3'h2;8'b0000_001x:code=3'h1;8'b0000_000x:code=3'h0;default:code=3'hx;endcaseendfunctionassigndout=code(din);//函數(shù)調(diào)用endmodule【例6.8】順序執(zhí)行模塊1moduleserial1(q,a,clk);outputq,a;inputclk;regq,a;always@(posedgeclk)beginq=~q;a=~q;endendmodule【例6.9】順序執(zhí)行模塊2moduleserial2(q,a,clk);outputq,a;程序文本-16-inputclk;regq,a;always@(posedgeclk)begina=~q;q=~q;endendmodule【例6.10】并行執(zhí)行模塊1moduleparal1(q,a,clk);outputq,a;inputclk;regq,a;always@(posedgeclk)beginq=~q;endalways@(posedgeclk)begina=~q;endendmodule【例6.11】并行執(zhí)行模塊2moduleparal2(q,a,clk);outputq,a;inputclk;regq,a;always@(posedgeclk)begina=~q;endalways@(posedgeclk)beginq=~q;endendmodule【例7.1】調(diào)用門元件實(shí)現(xiàn)的4選1MUX-17-modulemux4_1a(out,in1,in2,in3,in4,cntrl1,cntrl2);outputout;inputin1,in2,in3,in4,cntrl1,cntrl2;wirenotcntrl1,notcntrl2,w,x,y,z;not(notcntrl1,cntrl2),(notcntrl2,cntrl2);and(w,in1,notcntrl1,notcntrl2),(x,in2,notcntrl1,cntrl2),(y,in3,cntrl1,notcntrl2),(z,in4,cntrl1,cntrl2);or(out,w,x,y,z);endmodule【例7.2】用case語句描述的4選1MUXmodulemux4_1b(out,in1,in2,in3,in4,cntrl1,cntrl2);outputout;inputin1,in2,in3,in4,cntrl1,cntrl2;regout;always@(in1orin2orin3orin4orcntrl1orcntrl2)case({cntrl1,cntrl2})2'b00:out=in1;2'b01:out=in2;2'b10:out=in3;2'b11:out=in4;default:out=2'bx;endcaseendmodule【例7.3】行為描述方式實(shí)現(xiàn)的4位計(jì)數(shù)器modulecount4(clk,clr,out);inputclk,clr;output[3:0]out;reg[3:0]out;always@(posedgeclkorposedgeclr)beginif(clr)out<=0;elseout<=out+1;endendmodule程序文本-18-【例7.4】數(shù)據(jù)流方式描述的4選1MUXmodulemux4_1c(out,in1,in2,in3,in4,cntrl1,cntrl2);outputout;inputin1,in2,in3,in4,cntrl1,cntrl2;assignout=(in1&~cntrl1&~cntrl2)|(in2&~cntrl1&cntrl2)|(in3&cntrl1&~cntrl2)|(in4&cntrl1&cntrl2);Endmodule【例7.5】用條件運(yùn)算符描述的4選1MUXmodulemux4_1d(out,in1,in2,in3,in4,cntrl1,cntrl2);outputout;inputin1,in2,in3,in4,cntrl1,cntrl2;assignout=cntrl1?(cntrl2?in4:in3):(cntrl2?in2:in1);endmodule【例7.6】門級結(jié)構(gòu)描述的2選1MUXmodulemux2_1a(out,a,b,sel);outputout;inputa,b,sel;not(sel_,sel);and(a1,a,sel_),(a2,b,sel);or(out,a1,a2);endmodule【例7.7】行為描述的2選1MUXmodulemux2_1b(out,a,b,sel);outputout;inputa,b,sel;regout;always@(aorborsel)beginif(sel)out=b;elseout=a;endendmodule【例7.8】數(shù)據(jù)流描述的2選1MUXmoduleMUX2_1c(out,a,b,sel);outputout;-19-inputa,b,sel;assignout=sel?b:a;endmodule【例7.9】調(diào)用門元件實(shí)現(xiàn)的1位半加器modulehalf_add1(a,b,sum,cout);inputa,b;outputsum,cout;and(cout,a,b);xor(sum,a,b);endmodule【例7.10】數(shù)據(jù)流方式描述的1位半加器modulehalf_add2(a,b,sum,cout);inputa,b;outputsum,cout;assignsum=a^b;assigncout=a&b;endmodule【例7.11】采用行為描述的1位半加器modulehalf_add3(a,b,sum,cout);inputa,b;outputsum,cout;regsum,cout;always@(aorb)begincase({a,b})//真值表描述2'b00:beginsum=0;cout=0;end2'b01:beginsum=1;cout=0;end2'b10:beginsum=1;cout=0;end2'b11:beginsum=0;cout=1;endendcaseendendmodule【例7.12】采用行為描述的1位半加器modulehalf_add4(a,b,sum,cout);inputa,b;outputsum,cout;程序文本-20-regsum,cout;always@(aorb)beginsum=a^b;cout=a&b;endendmodule【例7.13】調(diào)用門元件實(shí)現(xiàn)的1位全加器modulefull_add1(a,b,cin,sum,cout);inputa,b,cin;outputsum,cout;wires1,m1,m2,m3;and(m1,a,b),(m2,b,cin),(m3,a,cin);xor(s1,a,b),(sum,s1,cin);or(cout,m1,m2,m3);endmodule【例7.14】數(shù)據(jù)流描述的1位全加器modulefull_add2(a,b,cin,sum,cout);inputa,b,cin;outputsum,cout;assignsum=a^b^cin;assigncout=(a&b)|(b&cin)|(cin&a);endmodule【例7.15】1位全加器modulefull_add3(a,b,cin,sum,cout);inputa,b,cin;outputsum,cout;assign{cout,sum}=a+b+cin;endmodule【例7.16】行為描述的1位全加器modulefull_add4(a,b,cin,sum,cout);inputa,b,cin;outputsum,cout;-21-regsum,cout;//在always塊中被賦值的變量應(yīng)定義為reg型regm1,m2,m3;always@(aorborcin)beginsum=(a^b)^cin;m1=a&b;m2=b&cin;m3=a&cin;cout=(m1|m2)|m3;endendmodule【例7.17】混合描述的1位全加器modulefull_add5(a,b,cin,sum,cout);inputa,b,cin;outputsum,cout;regcout,m1,m2,m3;//在always塊中被賦值的變量應(yīng)定義為reg型wires1;xorx1(s1,a,b);//調(diào)用門元件always@(aorborcin)//always塊語句beginm1=a&b;m2=b&cin;m3=a&cin;cout=(m1|m2)|m3;endassignsum=s1^cin;//assign持續(xù)賦值語句endmodule【例7.18】結(jié)構(gòu)描述的4位級連全加器`include"full_add1.v"moduleadd4_1(sum,cout,a,b,cin);output[3:0]sum;outputcout;input[3:0]a,b;inputcin;full_add1f0(a[0],b[0],cin,sum[0],cin1);//級連描述full_add1f1(a[1],b[1],cin1,sum[1],cin2);full_add1f2(a[2],b[2],cin2,sum[2],cin3);程序文本-22-full_add1f3(a[3],b[3],cin3,sum[3],cout);endmodule【例7.19】數(shù)據(jù)流描述的4位全加器moduleadd4_2(cout,sum,a,b,cin);output[3:0]sum;outputcout;input[3:0]a,b;inputcin;assign{cout,sum}=a+b+cin;endmodule【例7.20】行為描述的4位全加器moduleadd4_3(cout,sum,a,b,cin);output[3:0]sum;outputcout;input[3:0]a,b;inputcin;reg[3:0]sum;regcout;always@(aorborcin)begin{cout,sum}=a+b+cin;endendmodule【例8.12】延遲定義塊舉例moduledelay(out,a,b,c);outputout;inputa,b,c;anda1(n1,a,b);oro1(out,c,n1);specify(a=>out)=2;(b=>out)=3;(c=>out)=1;-27-endspecifyendmodule【例8.13】激勵波形的描述'timescale1ns/1nsmoduletest1;regA,B,C;initialbegin//激勵波形描述A=0;B=1;C=0;#100C=1;#100A=1;B=0;#100A=0;#100C=0;#100$finish;endinitial$monitor($time,,,"A=%dB=%dC=%d",A,B,C);//顯示endmodule【例8.15】用always過程塊產(chǎn)生兩個時鐘信號moduletest2;regclk1,clk2;parameterCYCLE=100;alwaysbegin{clk1,clk2}=2'b10;#(CYCLE/4){clk1,clk2}=2'b01;#(CYCLE/4){clk1,clk2}=2'b11;#(CYCLE/4){clk1,clk2}=2'b00;#(CYCLE/4){clk1,clk2}=2'b10;endinitial$monitor($time,,,"clk1=%bclk2=%b",clk1,clk2);endmodule【例8.19】8位加法器的仿真程序`timescale1ns/1nsmoduleadd8_tp;//仿真模塊無端口列表reg[7:0]A,B;//輸入激勵信號定義為reg型regcin;wire[7:0]SUM;//輸出信號定義為wire型wirecout;parameterDELY=100;add8AD1(SUM,cout,A,B,cin);//調(diào)用測試對象initialbegin//激勵波形設(shè)定A=8'd0;B=8'd0;cin=1'b0;#DELYA=8'd100;B=8'd200;cin=1'b1;#DELYA=8'd200;B=8'd88;#DELYA=8'd210;B=8'd18;cin=1'b0;#DELYA=8'd12;B=8'd12;#DELYA=8'd100;B=8'd154;#DELYA=8'd255;B=8'd255;cin=1'b1;#DELY$finish;end//輸出格式定義initial$monitor($time,,,"%d+%d+%b={%b,%d}",A,B,cin,cout,SUM);endmodulemoduleadd8(SUM,cout,A,B,cin);//待測試的8位加法器模塊output[7:0]SUM;outputcout;input[7:0]A,B;inputcin;assign{cout,SUM}=A+B+cin;endmodule【例8.20】2選1多路選擇器的仿真`timescale1ns/1nsmodulemux_tp;rega,b,sel;wireout;程序文本-30-MUX2_1m1(out,a,b,sel);//調(diào)用待測試模塊initialbegina=1'b0;b=1'b0;sel=1'b0;#5sel=1'b1;#5a=1'b1;sel=1'b0;#5sel=1'b1;#5a=1'b0;b=1'b1;sel=1'b0;#5sel=1'b1;#5a=1'b1;b=1'b1;sel=1'b0;#5sel=1'b1;endinitial$monitor($time,,,"a=%bb=%bsel=%bout=%b",a,b,sel,out);endmodulemoduleMUX2_1(out,a,b,sel);//待測試的2選1MUX模塊inputa,b,sel;outputout;not#(0.4,0.3)(sel_,sel);//#(0.4,0.3)為門延時and#(0.7,0.6)(a1,a,sel_);and#(0.7,0.6)(a2,b,sel);or#(0.7,0.6)(out,a1,a2);endmodule【例8.21】8位計(jì)數(shù)器的仿真`timescale10ns/1nsmodulecounter8_tp;regclk,reset;//輸入激勵信號定義為reg型wire[7:0]qout;//輸出信號定義為wire型parameterDELY=100;counter8C1(qout,reset,clk);//調(diào)用測試對象always#(DELY/2)clk=~clk;//產(chǎn)生時鐘波形initialbegin//激勵波形定義clk=0;reset=0;-31-#DELYreset=1;#DELYreset=0;#(DELY*300)$finish;end//結(jié)果顯示initial$monitor($time,,,"clk=%dreset=%dqout=%d",clk,reset,qout);endmodulemodulecounter8(qout,reset,clk);//待測試的8位計(jì)數(shù)器模塊output[7:0]qout;inputclk,reset;reg[7:0]qout;always@(posedgeclk)beginif(reset)qout<=0;elseqout<=qout+1;endendmodule【例9.1】基本門電路的幾種描述方法（1）門級結(jié)構(gòu)描述modulegate1(F,A,B,C,D);inputA,B,C,D;outputF;nand(F1,A,B);//調(diào)用門元件and(F2,B,C,D);or(F,F1,F2);endmodule（2）數(shù)據(jù)流描述modulegate2(F,A,B,C,D);inputA,B,C,D;outputF;assignF=(A&B)|(B&C&D);//assign持續(xù)賦值endmodule（3）行為描述modulegate3(F,A,B,C,D);inputA,B,C,D;outputF;程序文本-32-regF;always@(AorBorCorD)//過程賦值beginF=(A&B)|(B&C&D);endendmodule【例9.2】用bufif1關(guān)鍵字描述的三態(tài)門moduletri_1(in,en,out);inputin,en;outputout;triout;bufif1b1(out,in,en);//注意三態(tài)門端口的排列順序endmodule【例9.3】用assign語句描述的三態(tài)門moduletri_2(out,in,en);outputout;inputin,en;assignout=en?in:'bz;//若en=1，則out=in；若en=0，則out為高阻態(tài)Endmodule【例9.4】三態(tài)雙向驅(qū)動器modulebidir(tri_inout,out,in,en,b);inouttri_inout;outputout;inputin,en,b;assigntri_inout=en?in:'bz;assignout=tri_inout^b;endmodule【例9.5】三態(tài)雙向驅(qū)動器modulebidir2(bidir,en,clk);inout[7:0]bidir;inputen,clk;reg[7:0]temp;assignbidir=en?temp:8'bz;always@(posedgeclk)begin-33-if(en)temp=bidir;elsetemp=temp+1;endendmodule【例9.6】3-8譯碼器moduledecoder_38(out,in);output[7:0]out;input[2:0]in;reg[7:0]out;always@(in)begincase(in)3'd0:out=8'b11111110;3'd1:out=8'b11111101;3'd2:out=8'b11111011;3'd3:out=8'b11110111;3'd4:out=8'b11101111;3'd5:out=8'b11011111;3'd6:out=8'b10111111;3'd7:out=8'b01111111;endcaseendendmodule【例9.7】8-3優(yōu)先編碼器moduleencoder8_3(none_on,outcode,a,b,c,d,e,f,g,h);outputnone_on;output[2:0]outcode;inputa,b,c,d,e,f,g,h;reg[3:0]outtemp;assign{none_on,outcode}=outtemp;always@(aorborcordoreorforgorh)beginif(h)outtemp=4'b0111;elseif(g)outtemp=4'b0110;elseif(f)outtemp=4'b0101;elseif(e)outtemp=4'b0100;elseif(d)outtemp=4'b0011;elseif(c)outtemp=4'b0010;程序文本-34-elseif(b)outtemp=4'b0001;elseif(a)outtemp=4'b0000;elseouttemp=4'b1000;endendmodule【例9.8】用函數(shù)定義的8-3優(yōu)先編碼器modulecode_83(din,dout);input[7:0]din;output[2:0]dout;function[2:0]code;//函數(shù)定義input[7:0]din;//函數(shù)只有輸入端口，輸出為函數(shù)名本身if(din[7])code=3'd7;elseif(din[6])code=3'd6;elseif(din[5])code=3'd5;elseif(din[4])code=3'd4;elseif(din[3])code=3'd3;elseif(din[2])code=3'd2;elseif(din[1])code=3'd1;elsecode=3'd0;endfunctionassigndout=code(din);//函數(shù)調(diào)用endmodule【例9.10】奇偶校驗(yàn)位產(chǎn)生器moduleparity(even_bit,odd_bit,input_bus);outputeven_bit,odd_bit;input[7:0]input_bus;assignodd_bit=^input_bus;//產(chǎn)生奇校驗(yàn)位assigneven_bit=~odd_bit;//產(chǎn)生偶校驗(yàn)位endmodule【例9.11】用if-else語句描述的4選1MUXmodulemux_if(out,in0,in1,in2,in3,sel);outputout;inputin0,in1,in2,in3;input[1:0]sel;regout;always@(in0orin1orin2orin3orsel)beginif(sel==2'b00)out=in0;elseif(sel==2'b01)out=in1;elseif(sel==2'b10)out=in2;elseout=in3;endendmodule【例9.12】用case語句描述的4選1MUXmodulemux_case(out,in0,in1,in2,in3,sel);outputout;inputin0,in1,in2,in3;input[1:0]sel;regout;always@(in0orin1orin2orin3orsel)begin程序文本-36-case(sel)2'b00:out=in0;2'b01:out=in1;2'b10:out=in2;default:out=in3;endcaseendendmodule【例9.14】基本D觸發(fā)器-37-moduleDFF(Q,D,CLK);outputQ;inputD,CLK;regQ;always@(posedgeCLK)beginQ<=D;endendmodule【例9.15】帶異步清0、異步置1的D觸發(fā)器moduleDFF1(q,qn,d,clk,set,reset);inputd,clk,set,reset;outputq,qn;regq,qn;always@(posedgeclkornegedgesetornegedgereset)beginif(!reset)beginq<=0;//異步清0，低電平有效qn<=1;endelseif(!set)beginq<=1;//異步置1，低電平有效qn<=0;endelsebeginq<=d;qn<=~d;endendendmodule【例9.16】帶同步清0、同步置1的D觸發(fā)器moduleDFF2(q,qn,d,clk,set,reset);inputd,clk,set,reset;outputq,qn;regq,qn;always@(posedgeclk)beginif(reset)begin程序文本-38-q<=0;qn<=1;//同步清0，高電平有效endelseif(set)beginq<=1;qn<=0;//同步置1，高電平有效endelsebeginq<=d;qn<=~d;endendendmodule【例9.17】帶異步清0、異步置1的JK觸發(fā)器moduleJK_FF(CLK,J,K,Q,RS,SET);inputCLK,J,K,SET,RS;outputQ;regQ;always@(posedgeCLKornegedgeRSornegedgeSET)beginif(!RS)Q<=1'b0;elseif(!SET)Q<=1'b1;elsecase({J,K})2'b00:Q<=Q;2'b01:Q<=1'b0;2'b10:Q<=1'b1;2'b11:Q<=~Q;default:Q<=1'bx;endcaseendendmodule【例9.18】電平敏感的1位數(shù)據(jù)鎖存器modulelatch_1(q,d,clk);outputq;inputd,clk;assignq=clk?d:q;//時鐘信號為高電平時，將輸入端數(shù)據(jù)鎖存endmodule【例9.19】帶置位和復(fù)位端的1位數(shù)據(jù)鎖存器modulelatch_2(q,d,clk,set,reset);outputq;-39-inputd,clk,set,reset;assignq=reset?0:(set?1:(clk?d:q));endmodule【例9.20】8位數(shù)據(jù)鎖存器modulelatch_8(qout,data,clk);output[7:0]qout;input[7:0]data;inputclk;reg[7:0]qout;always@(clkordata)beginif(clk)qout<=data;endendmodule【例9.21】8位數(shù)據(jù)寄存器modulereg8(out_data,in_data,clk,clr);output[7:0]out_data;input[7:0]in_data;inputclk,clr;reg[7:0]out_data;always@(posedgeclkorposedgeclr)beginif(clr)out_data<=0;elseout_data<=in_data;endendmodule【例9.22】8位移位寄存器moduleshifter(din,clk,clr,dout);inputdin,clk,clr;output[7:0]dout;reg[7:0]dout;always@(posedgeclk)beginif(clr)dout<=8'b0;//同步清0，高電平有效elsebegindout<=dout<<1;//輸出信號左移一位程序文本-40-dout[0]<=din;//輸入信號補(bǔ)充到輸出信號的最低位endendendmodule【例9.24】4位Johnson計(jì)數(shù)器（異步復(fù)位）modulejohnson(clk,clr,out);inputclk,clr;output[3:0]out;reg[3:0]out;always@(posedgeclkorposedgeclr)beginif(clr)out<=4'h0;elsebeginout<=out<<1;out[0]<=~out[3];endendendmodule【例9.25】256×8RAM模塊moduleram256x8(data,address,we,inclock,outclock,q);input[7:0]data;-41-input[7:0]address;inputwe,inclock,outclock;output[7:0]q;lpm_ram_dqmyram(.q(q),.data(data),.address(address),.we(we),.inclock(inclock),.outclock(outclock));defparammyram.lpm_width=8;//定義數(shù)據(jù)寬度defparammyram.lpm_widthad=8;//定義地址寬度endmodule【例9.26】256×16RAM塊modulemap_lpm_ram(dataout,datain,addr,we,inclk,outclk);input[15:0]datain;//端口定義input[7:0]addr;inputwe,inclk,outclk;output[15:0]dataout;//lpm_ram_dq元件例化lpm_ram_dqram(.data(datain),.address(addr),.we(we),.inclock(inclk),.outclock(outclk),.q(dataout));defparamram.lpm_width=16;//參數(shù)賦值defparamram.lpm_widthad=8;defparamram.lpm_indata="REGISTERED";defparamram.lpm_outdata="REGISTERED";defparamram.lpm_file="map_lpm_ram.mif";//RAM塊中的內(nèi)容取自該文件endmodule【例10.1】非流水線方式8位全加器moduleadder8(cout,sum,ina,inb,cin,clk);output[7:0]sum;outputcout;input[7:0]ina,inb;inputcin,clk;reg[7:0]tempa,tempb,sum;regcout;regtempc;always@(posedgeclk)begintempa=ina;tempb=inb;tempc=cin;//輸入數(shù)據(jù)鎖存endalways@(posedgeclk)begin{cout,sum}=tempa+tempb+tempc;endendmodule【例10.3】兩個加法器和一個選擇器的實(shí)現(xiàn)方式moduleresource1(sum,a,b,c,d,sel);parametersize=4;output[size:0]sum;-47-inputsel;input[size-1:0]a,b,c,d;reg[size:0]sum;always@(aorborcordorsel)beginif(sel)sum=a+b;elsesum=c+d;endendmodule【例10.4】兩個選擇器和一個加法器的實(shí)現(xiàn)方式moduleresource2(sum,a,b,c,d,sel);parametersize=4;output[size-1:0]sum;inputsel;input[size-1:0]a,b,c,d;reg[size-1:0]atemp,btemp;reg[size:0]sum;always@(aorborcordorsel)beginif(sel)beginatemp=a;btemp=b;endelsebeginatemp=c;btemp=d;endsum=atemp+btemp;endendmodule【例10.5】狀態(tài)機(jī)設(shè)計(jì)的例子moduleFSM(clk,clr,out,start,step2,step3);inputclk,clr,start,step2,step3;output[2:0]out;reg[2:0]out;reg[1:0]state,next_state;parameterstate0=2'b00,state1=2'b01,state2=2'b11,state3=2'b10;/*狀態(tài)編碼，采用格雷（Gray）編碼方式*/always@(posedgeclkorposedgeclr)/*該進(jìn)程定義起始狀態(tài)*/beginif(clr)state<=state0;elsestate<=next_state;程序文本-48-endalways@(stateorstartorstep2orstep3)/*該進(jìn)程實(shí)現(xiàn)狀態(tài)的轉(zhuǎn)換*/begincase(state)state0:beginif(start)next_state<=state1;elsenext_state<=state0;endstate1:beginnext_state<=state2;endstate2:beginif(step2)next_state<=state3;elsenext_state<=state0;endstate3:beginif(step3)next_state<=state0;elsenext_state<=state3;enddefault:next_state<=state0;/*default語句*/endcaseendalways@(state)/*該進(jìn)程定義組合邏輯（FSM的輸出）*/begincase(state)state0: