1、實驗名稱 移位寄存器設計一：實驗目的二：實驗所用儀表及主要器材三：實驗原理簡述（源程序、真值表、原理圖）四：實驗測量記錄（數(shù)據(jù)、仿真波形圖及分析、源程序分析、硬件測試實時分析）五：實驗心得（實驗中問題的解決方法等）一：實驗目的(1)掌握移位寄存器電路設計的方法。(2)通過開發(fā)CPLD來實現(xiàn)時序邏輯電路的功能。二：實驗所用儀表及主要器材 Max+plus2軟件。三：實驗原理簡述（源程序、真值表、原理圖）（1）環(huán)形計數(shù)器源程序：library IEEE;use IEEE.std_logic_1164.all;entity huanxing is port ( clk : in std_logic;

2、 load : in std_logic; d : in std_logic_vector(3 downto 0); q : out std_logic_vector(3 downto 0);end entity;architecture shft_reg_arch of huanxing issignal TEMP : std_logic_vector(3 downto 0);beginprocess(clk) begin if clk'event and clk='1' then if load = '1' then TEMP <= d; el

3、sif TEMP="1000" then TEMP<= TEMP(0) & TEMP(3 downto 1); elsif TEMP="0100" then TEMP<= TEMP(0) & TEMP(3 downto 1); elsif TEMP="0010" then TEMP<= TEMP(0) & TEMP(3 downto 1); elsif TEMP="0001" then TEMP<= TEMP(0) & TEMP(3 downto 1); el

4、se TEMP<="1000" end if; end if; end process; q <= TEMP;end architecture;（2）節(jié)日彩燈 源程序：library IEEE;use IEEE.std_logic_1164.all;entity caideng is port ( clk : in std_logic; shift : in std_logic; q : out std_logic_vector(3 downto 0);end entity;architecture shft_reg_arch of caideng issign

5、al temp : std_logic_vector(3 downto 0);begin q<=temp; process(clk) begin if (clk'event and clk='1') then if shift='1' then case temp is when "0000"=>temp<="1000" when "1000"=>temp<="1100" when "1100"=>temp<=&q

6、uot;1110" when "1110"=>temp<="1111" when "1111"=>temp<="0111" when "0111"=>temp<="0011" when "0011"=>temp<="0001" when "0001"=>temp<="0000" when others=>temp<=

7、"0000" end case; else case temp is when "0000"=>temp<="0001" when "0001"=>temp<="0011" when "0011"=>temp<="0111" when "0111"=>temp<="1111" when "1111"=>temp<="1110" when "1110"=>temp<="1100" when "1100"=>temp<="1000" when "1000"=>temp<="0000" when others=>temp<="0000" end case; end if; end if; end process ;end architecture;狀態(tài)轉(zhuǎn)換圖：當shift=1時當shift=0時四：實驗測量記錄（數(shù)據(jù)、