1、spi四種模式SPI的相位(CPHA)和極性(CPOL)分別可以為0或1，對(duì)應(yīng)的4種組合構(gòu)成了SPI的4種模式(mode)Mode 0 CPOL=0, CPHA=0Mode 1 CPOL=0, CPHA=1Mode 2 CPOL=1, CPHA=0Mode 3 CPOL=1, CPHA=1時(shí)鐘極性CPOL: 即SPI空閑時(shí)，時(shí)鐘信號(hào)SCLK的電平（1:空閑時(shí)高電平; 0:空閑時(shí)低電平）時(shí)鐘相位CPHA: 即SPI在SCLK第幾個(gè)邊沿開(kāi)始采樣（0:第一個(gè)邊沿開(kāi)始; 1:第二個(gè)邊沿開(kāi)始）sd卡地spi常用的是mode 0 和mode 3，這兩種模式的相同的地方是都在時(shí)鐘上升沿采樣傳輸數(shù)據(jù)，區(qū)別這兩

2、種方式的簡(jiǎn)單方法就是看空閑時(shí)，時(shí)鐘的電平狀態(tài)，低電平為mode 0 ，高電平為mode 3。OverviewThe SPI standard includes four modes, defined by the polarity of SCLK and the phase relationship between data and SCLK. The clock polarity (CPOL) is determined by the idle state of SCLK. If the idle state is low, CPOL is 0. If the idle state is h

3、igh, CPOL is 1. The clock phase (CPHA) is determined by which edge that data is valid. If the data is valid on the first edge of SCLK, CPHA is 0. If the data is valid on the second edge of SCLK, CPHA is 1.Industry has two common formats to define the four SPI modes. The first format defines the four

4、 possible combinations of phase and polarity as mode 0, mode 1, mode 2, and mode 3. The second format defines the combinations as mode 0,0, mode 0,1, mode 1,0, and mode 1,1. The SPI master must use a mode supported by the slave device to allow proper communications.Dallas Semiconductor/Maxims SPI-in

5、terface RTCs support both SCLK polarities. The RTC automatically determines the polarity by detecting the idle state of SCLK when CE is asserted. The master must, therefore, place SCLK in the proper idle state before CE is asserted. Only one phase is supported. Since two SCLK polarities are supporte

6、d, two of the four SPI modes are supported by the RTCs: modes 1 and 3 (mode 0,1 and mode 1,1).On microcontrollers with built-in SPI interfaces, an SPI control or configuration register will have bits that control the polarity and phase. Because the RTC supports either polarity, the polarity can be s

7、et as desired. The phase bit, however, must be set properly, or the RTC will not operate correctly.Figure 1 shows a typical single-byte read and Figure 2 shows a typical single-byte write. Each time CE is asserted, the first eight SCLK pulses are used to clock in a command byte. The command byte con

8、sists of several bits that define a register address, and one bit that defines the data direction: a write if the next eight SCLK pulses will clock data into the part, or a read if data is clocked out of the part. Additional groups of eight SCLK pulses continue to transfer data in the selected direc

9、tion until CE is deasserted.2 / 4Note: In burst mode, CE is kept high and additional SCLK cycles are sent until the end of the burst.Figure 1. Single-byte read.Note: In burst mode, CE is kept high and additional SCLK cycles are sent until the end of the burst.Figure 2. Single-byte write.Examples of SPI code are available