基于stm32f4的ov2640攝像頭模塊lcd圖像傳輸Lcd

image

display

of

ov2640

camera

modulebased

on

stm32f4STMicroelectronics

introduced

the

STM32F4

family

of

high-performance

microcontrollers

based

on

the

ARM?

Cortex

?

-M4

coreusing

a

90-nm

NVM

process

and

ART

(Adaptive

Real-Time

MemoryAccelerator

?

).ART

technology

makes

the

program

no

wait

for

execution,

improve

theefficiency

of

program

execution,

making

the

STM32

F4

series

can

reach210DMIPS

@

168MHz.The

STM32F4

family

of

microcontrollers

integrates

single-cycle

DSPinstructions

and

FPU

(floating

point

unit)

to

improve

computational

powand

allow

for

complex

calculations

and

controls.Introduction

of

STM32F4This

section

applies

to

the

whole

STM32F4xx

family

devices,

unlessotherwise

specified.The

digital

camera

is

a

synchronous

parallel

interface

able

to

receivhigh-speed

data

flow

from

an

external

8-,

10-,

12-

or

14-bit

CMOS

camera

module.

It

supports

different

data

formats:

YCbCr4:2:2/RGB565progressive

video

and

compressed

data

(JPEG).This

interface

is

for

use

with

black

&

white

cameras,

X24

and

X5cameras,

and

it

is

assumed

that

all

pre-processing

like

resizing

isperformed

in

the

camera

module.Introduction

of

DCMI

of

STM32F4DCMI

main

features8-,

10-,

12-

or

14-bit

parallel

interfaceEmbedded/external

line

and

frame

synchronizationContinuous

or

snapshot

modeCrop

featureSupports

the

following

data

formats:–

8/10/12/14-

bit

progressive

video:

eithermonochrome

or

raw

bayerYCbCr

4:2:2

progressive

videoRGB

565

progressive

videoCompressed

data:

JPEGDCMI

pinsTable

shows

the

DCMI

pinsTable

DCMIName

pinsSignal

typeD[0:13]Data

inputsHSYNCHorizontal

synchronization

inputVSYNCVertical

synchronization

inputPIXCLKPixel

clock

inputThe

digital

camera

interface

uses

two

clock

domains

PIXCLK

and

HCLK.The

signals

generated

with

PIXCLK

are

sampled

on

the

rising

edge

ofHCLK

once

they

are

stable.

Anenable

signal

is

generated

in

the

HCLKdomain,

to

indicate

that

data

coming

from

the

camera

are

stable

and

canbe

sampled.

The

minimum

PIXCLK

period

must

be

higher

than

2.5

HCLKperiods.DCMI

clocksDCMI

functional

overviewThe

digital

camera

interface

is

a

synchronous

parallel

interface

that

receive

high-speed

(up

to

54

Mbytes/s)

data

flows.

It

consists

of

up

to

1lines(D13-D0)

and

a

pixel

clock

line

(PIXCLK).The

pixel

clock

has

a

programmable

polarity,

so

that

data

can

be

captu

on

either

the

rising

or

the

falling

edge

of

the

pixel

clock.The

data

are

packed

into

a

32-bit

data

register

(DCMI_DR)

and

then

tra

ferred

through

a

general-purpose

DMA

channel

.The

image

buffer

is

managed

by

the

DMA,

not

by

the

camera

interface.The

data

received

from

the

camera

can

be

organized

in

lines/frames

(raYUB/RGB/Bayer

modes)

or

can

be

a

sequence

of

JPEG

images.

To

enableJPEG

image

reception,

the

JPEG

bit

(bit

3

of

DCMI_CR

register)

must

be

se

The

data

flow

is

synchronized

either

by

hardware

using

the

optional

HSYN

(horizontal

synchronization)

and

VSYNC

(vertical

synchronization)

sign

by

synchronization

codesembedded

in

the

data

flow.DCMI

block

diagramTop-level

block

diagramDMA

interfaceThe

DMA

interface

is

active

when

the

CAPTURE

bit

in

the

DCMI_CR

register

is

set.

A

DMA

request

is

generated

each

time

the

camera

interface

receives

a

com

ete

32-bit

data

block

in

its

register.DCMIphysical

interfaceThe

interface

is

composed

of

11/13/15/17

inputs.

Only

the

Slave

modeis

supported.The

camera

interface

can

capture

8-bit,

10-bit,

12-bit

or

14-bit

datadepending

on

the

EDM[1:0]

bits

in

the

DCMI_CR

register.

If

less

than

14bits

are

used,

the

unused

data

pins

must

not

be

assigned

to

DCMI

interface

through

GPIO

alternate

functions.DCMI

signalsDCMI

signal

waveformsIntroduction

of

OV2640

sensorImage

sensor

is

the

core

of

the

camera,

the

camera

in

the

imagesensor

is

a

model

OV2640

CMOS

type

digital

image

sensor.

The

sensorsupports

output

of

up

to

2

megapixel

images

(1600x1200

pointsResolution),

support

the

use

of

VGA

timing

output

image

data,

the

outputimage

data

format

support

YUV

(422/420),

YCbCr422,RGB565,

and

JPEG

formats,

data

can

be

greatly

reduced

if

images

areoutput

directly

in

JPEG

format

Volume,

convenient

network

transmission.It

also

compensates

for

captured

images,

supporting

gamma

curves,white

balance,

and

saturation

Degree,

color

and

other

basictreatment.

According

to

the

different

resolution

configuration,

the

sensoutput

image

data

frame

rate

from

15-60

framesTune,

the

work

of

power

between

125mW-140mW.pin

and

functional

block

diagram

of

OV2640OV2640

sensor

using

BGA

package,

it"s

front-end

lighting

window,

the

pin

leads

tthe

back,

the

pin

pointsSee

Figure

for

cloth.Below

we

cooperate

with

the

OV2640

functional

block

diagram

inabove

Figure

to

explain

these

signal

pins.hardware

designCamera

schematicThe

experiment

used

OV2640

camera

schematic

diagram

is

as